|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc19606 { 3544, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3544 = V_DIV_FIXUP_F16
19607 { 3545, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10b40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3545 = V_DIV_FIXUP_F16_gfx9
19679 { 3617, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3617 = V_FMA_F16
19680 { 3618, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10b40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3618 = V_FMA_F16_gfx9
19797 { 3735, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10b00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3735 = V_MAD_F16
19798 { 3736, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3736 = V_MAD_F16_gfx9
19814 { 3752, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3752 = V_MAX3_F16
19853 { 3791, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3791 = V_MED3_F16
19879 { 3817, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3817 = V_MIN3_F16
30039 { 13977, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10b40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #13977 = V_DIV_FIXUP_F16_gfx10
30040 { 13978, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10b40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #13978 = V_DIV_FIXUP_F16_gfx9_gfx9
30041 { 13979, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #13979 = V_DIV_FIXUP_F16_vi
30048 { 13986, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #13986 = V_DIV_FIXUP_LEGACY_F16_gfx9
30198 { 14136, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10b40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14136 = V_FMA_F16_gfx10
30199 { 14137, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10b40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14137 = V_FMA_F16_gfx9_gfx9
30200 { 14138, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14138 = V_FMA_F16_vi
30207 { 14145, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14145 = V_FMA_LEGACY_F16_gfx9
30454 { 14392, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14392 = V_MAD_F16_gfx9_gfx9
30455 { 14393, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10b00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14393 = V_MAD_F16_vi
30470 { 14408, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10b00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14408 = V_MAD_LEGACY_F16_gfx9
30490 { 14428, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14428 = V_MAX3_F16_gfx10
30491 { 14429, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14429 = V_MAX3_F16_vi
30576 { 14514, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14514 = V_MED3_F16_gfx10
30577 { 14515, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14515 = V_MED3_F16_vi
30611 { 14549, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14549 = V_MIN3_F16_gfx10
30612 { 14550, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #14550 = V_MIN3_F16_vi