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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc19558 { 3496, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #3496 = V_CVT_I16_F16_sdwa
19568 { 3506, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #3506 = V_CVT_NORM_I16_F16_sdwa
19572 { 3510, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #3510 = V_CVT_NORM_U16_F16_sdwa
19599 { 3537, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #3537 = V_CVT_U16_F16_sdwa
19699 { 3637, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #3637 = V_FREXP_EXP_I16_F16_sdwa
29915 { 13853, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13853 = V_CVT_I16_F16_sdwa_gfx10
29916 { 13854, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13854 = V_CVT_I16_F16_sdwa_gfx9
29917 { 13855, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13855 = V_CVT_I16_F16_sdwa_vi
29943 { 13881, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13881 = V_CVT_NORM_I16_F16_sdwa_gfx10
29944 { 13882, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13882 = V_CVT_NORM_I16_F16_sdwa_gfx9
29945 { 13883, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13883 = V_CVT_NORM_I16_F16_sdwa_vi
29953 { 13891, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13891 = V_CVT_NORM_U16_F16_sdwa_gfx10
29954 { 13892, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13892 = V_CVT_NORM_U16_F16_sdwa_gfx9
29955 { 13893, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13893 = V_CVT_NORM_U16_F16_sdwa_vi
30018 { 13956, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13956 = V_CVT_U16_F16_sdwa_gfx10
30019 { 13957, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13957 = V_CVT_U16_F16_sdwa_gfx9
30020 { 13958, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #13958 = V_CVT_U16_F16_sdwa_vi
30249 { 14187, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #14187 = V_FREXP_EXP_I16_F16_sdwa_gfx10
30250 { 14188, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #14188 = V_FREXP_EXP_I16_F16_sdwa_gfx9
30251 { 14189, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #14189 = V_FREXP_EXP_I16_F16_sdwa_vi