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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc19499 { 3437, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3437 = V_CUBEID_F32
19500 { 3438, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3438 = V_CUBEMA_F32
19501 { 3439, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3439 = V_CUBESC_F32
19502 { 3440, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3440 = V_CUBETC_F32
19608 { 3546, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3546 = V_DIV_FIXUP_F32
19610 { 3548, 9, 1, 8, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList13, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3548 = V_DIV_FMAS_F32
19681 { 3619, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3619 = V_FMA_F32
19799 { 3737, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3737 = V_MAD_F32
19805 { 3743, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3743 = V_MAD_LEGACY_F32
19815 { 3753, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3753 = V_MAX3_F32
19854 { 3792, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3792 = V_MED3_F32
19880 { 3818, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3818 = V_MIN3_F32
19941 { 3879, 9, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3879 = V_MULLIT_F32
29744 { 13682, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13682 = V_CUBEID_F32_gfx10
29745 { 13683, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13683 = V_CUBEID_F32_gfx6_gfx7
29746 { 13684, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13684 = V_CUBEID_F32_vi
29747 { 13685, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13685 = V_CUBEMA_F32_gfx10
29748 { 13686, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13686 = V_CUBEMA_F32_gfx6_gfx7
29749 { 13687, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13687 = V_CUBEMA_F32_vi
29750 { 13688, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13688 = V_CUBESC_F32_gfx10
29751 { 13689, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13689 = V_CUBESC_F32_gfx6_gfx7
29752 { 13690, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13690 = V_CUBESC_F32_vi
29753 { 13691, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13691 = V_CUBETC_F32_gfx10
29754 { 13692, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13692 = V_CUBETC_F32_gfx6_gfx7
29755 { 13693, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13693 = V_CUBETC_F32_vi
30042 { 13980, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13980 = V_DIV_FIXUP_F32_gfx10
30043 { 13981, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13981 = V_DIV_FIXUP_F32_gfx6_gfx7
30044 { 13982, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13982 = V_DIV_FIXUP_F32_vi
30049 { 13987, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList13, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13987 = V_DIV_FMAS_F32_gfx10
30050 { 13988, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList13, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13988 = V_DIV_FMAS_F32_gfx6_gfx7
30051 { 13989, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList13, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #13989 = V_DIV_FMAS_F32_vi
30201 { 14139, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14139 = V_FMA_F32_gfx10
30202 { 14140, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14140 = V_FMA_F32_gfx6_gfx7
30203 { 14141, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14141 = V_FMA_F32_vi
30456 { 14394, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14394 = V_MAD_F32_gfx10
30457 { 14395, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14395 = V_MAD_F32_gfx6_gfx7
30458 { 14396, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14396 = V_MAD_F32_vi
30471 { 14409, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14409 = V_MAD_LEGACY_F32_gfx10
30472 { 14410, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14410 = V_MAD_LEGACY_F32_gfx6_gfx7
30473 { 14411, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14411 = V_MAD_LEGACY_F32_vi
30492 { 14430, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14430 = V_MAX3_F32_gfx10
30493 { 14431, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14431 = V_MAX3_F32_gfx6_gfx7
30494 { 14432, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14432 = V_MAX3_F32_vi
30578 { 14516, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14516 = V_MED3_F32_gfx10
30579 { 14517, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14517 = V_MED3_F32_gfx6_gfx7
30580 { 14518, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14518 = V_MED3_F32_vi
30613 { 14551, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14551 = V_MIN3_F32_gfx10
30614 { 14552, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14552 = V_MIN3_F32_gfx6_gfx7
30615 { 14553, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14553 = V_MIN3_F32_vi
30742 { 14680, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14680 = V_MULLIT_F32_gfx10
30743 { 14681, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #14681 = V_MULLIT_F32_gfx6_gfx7