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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18741 { 2679, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2679 = V_CMPX_EQ_I64_nosdst_e64
18757 { 2695, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2695 = V_CMPX_EQ_U64_nosdst_e64
18789 { 2727, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2727 = V_CMPX_F_I64_nosdst_e64
18805 { 2743, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2743 = V_CMPX_F_U64_nosdst_e64
18837 { 2775, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2775 = V_CMPX_GE_I64_nosdst_e64
18853 { 2791, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2791 = V_CMPX_GE_U64_nosdst_e64
18885 { 2823, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2823 = V_CMPX_GT_I64_nosdst_e64
18901 { 2839, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2839 = V_CMPX_GT_U64_nosdst_e64
18933 { 2871, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2871 = V_CMPX_LE_I64_nosdst_e64
18949 { 2887, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2887 = V_CMPX_LE_U64_nosdst_e64
18997 { 2935, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2935 = V_CMPX_LT_I64_nosdst_e64
19013 { 2951, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2951 = V_CMPX_LT_U64_nosdst_e64
19045 { 2983, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2983 = V_CMPX_NE_I64_nosdst_e64
19061 { 2999, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2999 = V_CMPX_NE_U64_nosdst_e64
19189 { 3127, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #3127 = V_CMPX_T_I64_nosdst_e64
19205 { 3143, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #3143 = V_CMPX_T_U64_nosdst_e64
28339 { 12277, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12277 = V_CMPX_EQ_I64_e64_gfx10
28361 { 12299, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12299 = V_CMPX_EQ_U64_e64_gfx10
28402 { 12340, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12340 = V_CMPX_F_I64_e64_gfx10
28421 { 12359, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12359 = V_CMPX_F_U64_e64_gfx10
28465 { 12403, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12403 = V_CMPX_GE_I64_e64_gfx10
28487 { 12425, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12425 = V_CMPX_GE_U64_e64_gfx10
28531 { 12469, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12469 = V_CMPX_GT_I64_e64_gfx10
28553 { 12491, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12491 = V_CMPX_GT_U64_e64_gfx10
28597 { 12535, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12535 = V_CMPX_LE_I64_e64_gfx10
28619 { 12557, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12557 = V_CMPX_LE_U64_e64_gfx10
28685 { 12623, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12623 = V_CMPX_LT_I64_e64_gfx10
28707 { 12645, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12645 = V_CMPX_LT_U64_e64_gfx10
28751 { 12689, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12689 = V_CMPX_NE_I64_e64_gfx10
28773 { 12711, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12711 = V_CMPX_NE_U64_e64_gfx10
28946 { 12884, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12884 = V_CMPX_T_I64_e64_gfx10
28965 { 12903, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #12903 = V_CMPX_T_U64_e64_gfx10