|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18739 { 2677, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2677 = V_CMPX_EQ_I64_e64
18755 { 2693, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2693 = V_CMPX_EQ_U64_e64
18787 { 2725, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2725 = V_CMPX_F_I64_e64
18803 { 2741, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2741 = V_CMPX_F_U64_e64
18835 { 2773, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2773 = V_CMPX_GE_I64_e64
18851 { 2789, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2789 = V_CMPX_GE_U64_e64
18883 { 2821, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2821 = V_CMPX_GT_I64_e64
18899 { 2837, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2837 = V_CMPX_GT_U64_e64
18931 { 2869, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2869 = V_CMPX_LE_I64_e64
18947 { 2885, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2885 = V_CMPX_LE_U64_e64
18995 { 2933, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2933 = V_CMPX_LT_I64_e64
19011 { 2949, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2949 = V_CMPX_LT_U64_e64
19043 { 2981, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2981 = V_CMPX_NE_I64_e64
19059 { 2997, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2997 = V_CMPX_NE_U64_e64
19187 { 3125, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #3125 = V_CMPX_T_I64_e64
19203 { 3141, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #3141 = V_CMPX_T_U64_e64
19245 { 3183, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3183 = V_CMP_EQ_I64_e64
19253 { 3191, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3191 = V_CMP_EQ_U64_e64
19269 { 3207, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3207 = V_CMP_F_I64_e64
19277 { 3215, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3215 = V_CMP_F_U64_e64
19293 { 3231, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3231 = V_CMP_GE_I64_e64
19301 { 3239, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3239 = V_CMP_GE_U64_e64
19317 { 3255, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3255 = V_CMP_GT_I64_e64
19325 { 3263, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3263 = V_CMP_GT_U64_e64
19341 { 3279, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3279 = V_CMP_LE_I64_e64
19349 { 3287, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3287 = V_CMP_LE_U64_e64
19373 { 3311, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3311 = V_CMP_LT_I64_e64
19381 { 3319, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3319 = V_CMP_LT_U64_e64
19397 { 3335, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3335 = V_CMP_NE_I64_e64
19405 { 3343, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3343 = V_CMP_NE_U64_e64
19469 { 3407, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3407 = V_CMP_T_I64_e64
19477 { 3415, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3415 = V_CMP_T_U64_e64
28340 { 12278, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12278 = V_CMPX_EQ_I64_e64_gfx6_gfx7
28341 { 12279, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12279 = V_CMPX_EQ_I64_e64_vi
28362 { 12300, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12300 = V_CMPX_EQ_U64_e64_gfx6_gfx7
28363 { 12301, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12301 = V_CMPX_EQ_U64_e64_vi
28403 { 12341, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12341 = V_CMPX_F_I64_e64_gfx6_gfx7
28404 { 12342, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12342 = V_CMPX_F_I64_e64_vi
28422 { 12360, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12360 = V_CMPX_F_U64_e64_gfx6_gfx7
28423 { 12361, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12361 = V_CMPX_F_U64_e64_vi
28466 { 12404, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12404 = V_CMPX_GE_I64_e64_gfx6_gfx7
28467 { 12405, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12405 = V_CMPX_GE_I64_e64_vi
28488 { 12426, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12426 = V_CMPX_GE_U64_e64_gfx6_gfx7
28489 { 12427, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12427 = V_CMPX_GE_U64_e64_vi
28532 { 12470, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12470 = V_CMPX_GT_I64_e64_gfx6_gfx7
28533 { 12471, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12471 = V_CMPX_GT_I64_e64_vi
28554 { 12492, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12492 = V_CMPX_GT_U64_e64_gfx6_gfx7
28555 { 12493, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12493 = V_CMPX_GT_U64_e64_vi
28598 { 12536, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12536 = V_CMPX_LE_I64_e64_gfx6_gfx7
28599 { 12537, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12537 = V_CMPX_LE_I64_e64_vi
28620 { 12558, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12558 = V_CMPX_LE_U64_e64_gfx6_gfx7
28621 { 12559, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12559 = V_CMPX_LE_U64_e64_vi
28686 { 12624, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12624 = V_CMPX_LT_I64_e64_gfx6_gfx7
28687 { 12625, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12625 = V_CMPX_LT_I64_e64_vi
28708 { 12646, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12646 = V_CMPX_LT_U64_e64_gfx6_gfx7
28709 { 12647, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12647 = V_CMPX_LT_U64_e64_vi
28752 { 12690, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12690 = V_CMPX_NE_I64_e64_gfx6_gfx7
28753 { 12691, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12691 = V_CMPX_NE_I64_e64_vi
28774 { 12712, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12712 = V_CMPX_NE_U64_e64_gfx6_gfx7
28775 { 12713, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12713 = V_CMPX_NE_U64_e64_vi
28947 { 12885, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12885 = V_CMPX_T_I64_e64_gfx6_gfx7
28948 { 12886, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12886 = V_CMPX_T_I64_e64_vi
28966 { 12904, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12904 = V_CMPX_T_U64_e64_gfx6_gfx7
28967 { 12905, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #12905 = V_CMPX_T_U64_e64_vi
29053 { 12991, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #12991 = V_CMP_EQ_I64_e64_gfx10
29054 { 12992, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #12992 = V_CMP_EQ_I64_e64_gfx6_gfx7
29055 { 12993, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #12993 = V_CMP_EQ_I64_e64_vi
29075 { 13013, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13013 = V_CMP_EQ_U64_e64_gfx10
29076 { 13014, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13014 = V_CMP_EQ_U64_e64_gfx6_gfx7
29077 { 13015, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13015 = V_CMP_EQ_U64_e64_vi
29116 { 13054, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13054 = V_CMP_F_I64_e64_gfx10
29117 { 13055, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13055 = V_CMP_F_I64_e64_gfx6_gfx7
29118 { 13056, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13056 = V_CMP_F_I64_e64_vi
29135 { 13073, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13073 = V_CMP_F_U64_e64_gfx10
29136 { 13074, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13074 = V_CMP_F_U64_e64_gfx6_gfx7
29137 { 13075, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13075 = V_CMP_F_U64_e64_vi
29179 { 13117, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13117 = V_CMP_GE_I64_e64_gfx10
29180 { 13118, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13118 = V_CMP_GE_I64_e64_gfx6_gfx7
29181 { 13119, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13119 = V_CMP_GE_I64_e64_vi
29201 { 13139, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13139 = V_CMP_GE_U64_e64_gfx10
29202 { 13140, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13140 = V_CMP_GE_U64_e64_gfx6_gfx7
29203 { 13141, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13141 = V_CMP_GE_U64_e64_vi
29245 { 13183, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13183 = V_CMP_GT_I64_e64_gfx10
29246 { 13184, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13184 = V_CMP_GT_I64_e64_gfx6_gfx7
29247 { 13185, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13185 = V_CMP_GT_I64_e64_vi
29267 { 13205, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13205 = V_CMP_GT_U64_e64_gfx10
29268 { 13206, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13206 = V_CMP_GT_U64_e64_gfx6_gfx7
29269 { 13207, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13207 = V_CMP_GT_U64_e64_vi
29311 { 13249, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13249 = V_CMP_LE_I64_e64_gfx10
29312 { 13250, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13250 = V_CMP_LE_I64_e64_gfx6_gfx7
29313 { 13251, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13251 = V_CMP_LE_I64_e64_vi
29333 { 13271, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13271 = V_CMP_LE_U64_e64_gfx10
29334 { 13272, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13272 = V_CMP_LE_U64_e64_gfx6_gfx7
29335 { 13273, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13273 = V_CMP_LE_U64_e64_vi
29399 { 13337, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13337 = V_CMP_LT_I64_e64_gfx10
29400 { 13338, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13338 = V_CMP_LT_I64_e64_gfx6_gfx7
29401 { 13339, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13339 = V_CMP_LT_I64_e64_vi
29421 { 13359, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13359 = V_CMP_LT_U64_e64_gfx10
29422 { 13360, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13360 = V_CMP_LT_U64_e64_gfx6_gfx7
29423 { 13361, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13361 = V_CMP_LT_U64_e64_vi
29465 { 13403, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13403 = V_CMP_NE_I64_e64_gfx10
29466 { 13404, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13404 = V_CMP_NE_I64_e64_gfx6_gfx7
29467 { 13405, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13405 = V_CMP_NE_I64_e64_vi
29487 { 13425, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13425 = V_CMP_NE_U64_e64_gfx10
29488 { 13426, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13426 = V_CMP_NE_U64_e64_gfx6_gfx7
29489 { 13427, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13427 = V_CMP_NE_U64_e64_vi
29660 { 13598, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13598 = V_CMP_T_I64_e64_gfx10
29661 { 13599, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13599 = V_CMP_T_I64_e64_gfx6_gfx7
29662 { 13600, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13600 = V_CMP_T_I64_e64_vi
29679 { 13617, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13617 = V_CMP_T_U64_e64_gfx10
29680 { 13618, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13618 = V_CMP_T_U64_e64_gfx6_gfx7
29681 { 13619, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #13619 = V_CMP_T_U64_e64_vi