|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18738 { 2676, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2676 = V_CMPX_EQ_I64_e32
18740 { 2678, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2678 = V_CMPX_EQ_I64_nosdst_e32
18754 { 2692, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2692 = V_CMPX_EQ_U64_e32
18756 { 2694, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2694 = V_CMPX_EQ_U64_nosdst_e32
18786 { 2724, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2724 = V_CMPX_F_I64_e32
18788 { 2726, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2726 = V_CMPX_F_I64_nosdst_e32
18802 { 2740, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2740 = V_CMPX_F_U64_e32
18804 { 2742, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2742 = V_CMPX_F_U64_nosdst_e32
18834 { 2772, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2772 = V_CMPX_GE_I64_e32
18836 { 2774, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2774 = V_CMPX_GE_I64_nosdst_e32
18850 { 2788, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2788 = V_CMPX_GE_U64_e32
18852 { 2790, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2790 = V_CMPX_GE_U64_nosdst_e32
18882 { 2820, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2820 = V_CMPX_GT_I64_e32
18884 { 2822, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2822 = V_CMPX_GT_I64_nosdst_e32
18898 { 2836, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2836 = V_CMPX_GT_U64_e32
18900 { 2838, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2838 = V_CMPX_GT_U64_nosdst_e32
18930 { 2868, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2868 = V_CMPX_LE_I64_e32
18932 { 2870, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2870 = V_CMPX_LE_I64_nosdst_e32
18946 { 2884, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2884 = V_CMPX_LE_U64_e32
18948 { 2886, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2886 = V_CMPX_LE_U64_nosdst_e32
18994 { 2932, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2932 = V_CMPX_LT_I64_e32
18996 { 2934, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2934 = V_CMPX_LT_I64_nosdst_e32
19010 { 2948, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2948 = V_CMPX_LT_U64_e32
19012 { 2950, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2950 = V_CMPX_LT_U64_nosdst_e32
19042 { 2980, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2980 = V_CMPX_NE_I64_e32
19044 { 2982, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2982 = V_CMPX_NE_I64_nosdst_e32
19058 { 2996, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2996 = V_CMPX_NE_U64_e32
19060 { 2998, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2998 = V_CMPX_NE_U64_nosdst_e32
19186 { 3124, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #3124 = V_CMPX_T_I64_e32
19188 { 3126, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #3126 = V_CMPX_T_I64_nosdst_e32
19202 { 3140, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #3140 = V_CMPX_T_U64_e32
19204 { 3142, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #3142 = V_CMPX_T_U64_nosdst_e32
19244 { 3182, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3182 = V_CMP_EQ_I64_e32
19252 { 3190, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3190 = V_CMP_EQ_U64_e32
19268 { 3206, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3206 = V_CMP_F_I64_e32
19276 { 3214, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3214 = V_CMP_F_U64_e32
19292 { 3230, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3230 = V_CMP_GE_I64_e32
19300 { 3238, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3238 = V_CMP_GE_U64_e32
19316 { 3254, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3254 = V_CMP_GT_I64_e32
19324 { 3262, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3262 = V_CMP_GT_U64_e32
19340 { 3278, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3278 = V_CMP_LE_I64_e32
19348 { 3286, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3286 = V_CMP_LE_U64_e32
19372 { 3310, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3310 = V_CMP_LT_I64_e32
19380 { 3318, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3318 = V_CMP_LT_U64_e32
19396 { 3334, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3334 = V_CMP_NE_I64_e32
19404 { 3342, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3342 = V_CMP_NE_U64_e32
19468 { 3406, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3406 = V_CMP_T_I64_e32
19476 { 3414, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3414 = V_CMP_T_U64_e32
28336 { 12274, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12274 = V_CMPX_EQ_I64_e32_gfx10
28337 { 12275, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12275 = V_CMPX_EQ_I64_e32_gfx6_gfx7
28338 { 12276, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12276 = V_CMPX_EQ_I64_e32_vi
28358 { 12296, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12296 = V_CMPX_EQ_U64_e32_gfx10
28359 { 12297, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12297 = V_CMPX_EQ_U64_e32_gfx6_gfx7
28360 { 12298, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12298 = V_CMPX_EQ_U64_e32_vi
28399 { 12337, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12337 = V_CMPX_F_I64_e32_gfx10
28400 { 12338, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12338 = V_CMPX_F_I64_e32_gfx6_gfx7
28401 { 12339, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12339 = V_CMPX_F_I64_e32_vi
28418 { 12356, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12356 = V_CMPX_F_U64_e32_gfx10
28419 { 12357, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12357 = V_CMPX_F_U64_e32_gfx6_gfx7
28420 { 12358, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12358 = V_CMPX_F_U64_e32_vi
28462 { 12400, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12400 = V_CMPX_GE_I64_e32_gfx10
28463 { 12401, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12401 = V_CMPX_GE_I64_e32_gfx6_gfx7
28464 { 12402, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12402 = V_CMPX_GE_I64_e32_vi
28484 { 12422, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12422 = V_CMPX_GE_U64_e32_gfx10
28485 { 12423, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12423 = V_CMPX_GE_U64_e32_gfx6_gfx7
28486 { 12424, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12424 = V_CMPX_GE_U64_e32_vi
28528 { 12466, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12466 = V_CMPX_GT_I64_e32_gfx10
28529 { 12467, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12467 = V_CMPX_GT_I64_e32_gfx6_gfx7
28530 { 12468, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12468 = V_CMPX_GT_I64_e32_vi
28550 { 12488, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12488 = V_CMPX_GT_U64_e32_gfx10
28551 { 12489, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12489 = V_CMPX_GT_U64_e32_gfx6_gfx7
28552 { 12490, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12490 = V_CMPX_GT_U64_e32_vi
28594 { 12532, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12532 = V_CMPX_LE_I64_e32_gfx10
28595 { 12533, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12533 = V_CMPX_LE_I64_e32_gfx6_gfx7
28596 { 12534, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12534 = V_CMPX_LE_I64_e32_vi
28616 { 12554, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12554 = V_CMPX_LE_U64_e32_gfx10
28617 { 12555, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12555 = V_CMPX_LE_U64_e32_gfx6_gfx7
28618 { 12556, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12556 = V_CMPX_LE_U64_e32_vi
28682 { 12620, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12620 = V_CMPX_LT_I64_e32_gfx10
28683 { 12621, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12621 = V_CMPX_LT_I64_e32_gfx6_gfx7
28684 { 12622, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12622 = V_CMPX_LT_I64_e32_vi
28704 { 12642, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12642 = V_CMPX_LT_U64_e32_gfx10
28705 { 12643, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12643 = V_CMPX_LT_U64_e32_gfx6_gfx7
28706 { 12644, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12644 = V_CMPX_LT_U64_e32_vi
28748 { 12686, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12686 = V_CMPX_NE_I64_e32_gfx10
28749 { 12687, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12687 = V_CMPX_NE_I64_e32_gfx6_gfx7
28750 { 12688, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12688 = V_CMPX_NE_I64_e32_vi
28770 { 12708, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12708 = V_CMPX_NE_U64_e32_gfx10
28771 { 12709, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12709 = V_CMPX_NE_U64_e32_gfx6_gfx7
28772 { 12710, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12710 = V_CMPX_NE_U64_e32_vi
28943 { 12881, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12881 = V_CMPX_T_I64_e32_gfx10
28944 { 12882, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12882 = V_CMPX_T_I64_e32_gfx6_gfx7
28945 { 12883, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12883 = V_CMPX_T_I64_e32_vi
28962 { 12900, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #12900 = V_CMPX_T_U64_e32_gfx10
28963 { 12901, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12901 = V_CMPX_T_U64_e32_gfx6_gfx7
28964 { 12902, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #12902 = V_CMPX_T_U64_e32_vi
29050 { 12988, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #12988 = V_CMP_EQ_I64_e32_gfx10
29051 { 12989, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #12989 = V_CMP_EQ_I64_e32_gfx6_gfx7
29052 { 12990, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #12990 = V_CMP_EQ_I64_e32_vi
29072 { 13010, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13010 = V_CMP_EQ_U64_e32_gfx10
29073 { 13011, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13011 = V_CMP_EQ_U64_e32_gfx6_gfx7
29074 { 13012, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13012 = V_CMP_EQ_U64_e32_vi
29113 { 13051, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13051 = V_CMP_F_I64_e32_gfx10
29114 { 13052, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13052 = V_CMP_F_I64_e32_gfx6_gfx7
29115 { 13053, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13053 = V_CMP_F_I64_e32_vi
29132 { 13070, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13070 = V_CMP_F_U64_e32_gfx10
29133 { 13071, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13071 = V_CMP_F_U64_e32_gfx6_gfx7
29134 { 13072, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13072 = V_CMP_F_U64_e32_vi
29176 { 13114, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13114 = V_CMP_GE_I64_e32_gfx10
29177 { 13115, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13115 = V_CMP_GE_I64_e32_gfx6_gfx7
29178 { 13116, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13116 = V_CMP_GE_I64_e32_vi
29198 { 13136, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13136 = V_CMP_GE_U64_e32_gfx10
29199 { 13137, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13137 = V_CMP_GE_U64_e32_gfx6_gfx7
29200 { 13138, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13138 = V_CMP_GE_U64_e32_vi
29242 { 13180, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13180 = V_CMP_GT_I64_e32_gfx10
29243 { 13181, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13181 = V_CMP_GT_I64_e32_gfx6_gfx7
29244 { 13182, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13182 = V_CMP_GT_I64_e32_vi
29264 { 13202, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13202 = V_CMP_GT_U64_e32_gfx10
29265 { 13203, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13203 = V_CMP_GT_U64_e32_gfx6_gfx7
29266 { 13204, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13204 = V_CMP_GT_U64_e32_vi
29308 { 13246, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13246 = V_CMP_LE_I64_e32_gfx10
29309 { 13247, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13247 = V_CMP_LE_I64_e32_gfx6_gfx7
29310 { 13248, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13248 = V_CMP_LE_I64_e32_vi
29330 { 13268, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13268 = V_CMP_LE_U64_e32_gfx10
29331 { 13269, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13269 = V_CMP_LE_U64_e32_gfx6_gfx7
29332 { 13270, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13270 = V_CMP_LE_U64_e32_vi
29396 { 13334, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13334 = V_CMP_LT_I64_e32_gfx10
29397 { 13335, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13335 = V_CMP_LT_I64_e32_gfx6_gfx7
29398 { 13336, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13336 = V_CMP_LT_I64_e32_vi
29418 { 13356, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13356 = V_CMP_LT_U64_e32_gfx10
29419 { 13357, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13357 = V_CMP_LT_U64_e32_gfx6_gfx7
29420 { 13358, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13358 = V_CMP_LT_U64_e32_vi
29462 { 13400, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13400 = V_CMP_NE_I64_e32_gfx10
29463 { 13401, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13401 = V_CMP_NE_I64_e32_gfx6_gfx7
29464 { 13402, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13402 = V_CMP_NE_I64_e32_vi
29484 { 13422, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13422 = V_CMP_NE_U64_e32_gfx10
29485 { 13423, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13423 = V_CMP_NE_U64_e32_gfx6_gfx7
29486 { 13424, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13424 = V_CMP_NE_U64_e32_vi
29657 { 13595, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13595 = V_CMP_T_I64_e32_gfx10
29658 { 13596, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13596 = V_CMP_T_I64_e32_gfx6_gfx7
29659 { 13597, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13597 = V_CMP_T_I64_e32_vi
29676 { 13614, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13614 = V_CMP_T_U64_e32_gfx10
29677 { 13615, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13615 = V_CMP_T_U64_e32_gfx6_gfx7
29678 { 13616, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #13616 = V_CMP_T_U64_e32_vi