|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18737 { 2675, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2675 = V_CMPX_EQ_I32_sdwa
18753 { 2691, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2691 = V_CMPX_EQ_U32_sdwa
18785 { 2723, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2723 = V_CMPX_F_I32_sdwa
18801 { 2739, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2739 = V_CMPX_F_U32_sdwa
18833 { 2771, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2771 = V_CMPX_GE_I32_sdwa
18849 { 2787, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2787 = V_CMPX_GE_U32_sdwa
18881 { 2819, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2819 = V_CMPX_GT_I32_sdwa
18897 { 2835, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2835 = V_CMPX_GT_U32_sdwa
18929 { 2867, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2867 = V_CMPX_LE_I32_sdwa
18945 { 2883, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2883 = V_CMPX_LE_U32_sdwa
18993 { 2931, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2931 = V_CMPX_LT_I32_sdwa
19009 { 2947, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2947 = V_CMPX_LT_U32_sdwa
19041 { 2979, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2979 = V_CMPX_NE_I32_sdwa
19057 { 2995, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2995 = V_CMPX_NE_U32_sdwa
19185 { 3123, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #3123 = V_CMPX_T_I32_sdwa
19201 { 3139, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #3139 = V_CMPX_T_U32_sdwa
19243 { 3181, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3181 = V_CMP_EQ_I32_sdwa
19251 { 3189, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3189 = V_CMP_EQ_U32_sdwa
19267 { 3205, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3205 = V_CMP_F_I32_sdwa
19275 { 3213, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3213 = V_CMP_F_U32_sdwa
19291 { 3229, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3229 = V_CMP_GE_I32_sdwa
19299 { 3237, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3237 = V_CMP_GE_U32_sdwa
19315 { 3253, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3253 = V_CMP_GT_I32_sdwa
19323 { 3261, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3261 = V_CMP_GT_U32_sdwa
19339 { 3277, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3277 = V_CMP_LE_I32_sdwa
19347 { 3285, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3285 = V_CMP_LE_U32_sdwa
19371 { 3309, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3309 = V_CMP_LT_I32_sdwa
19379 { 3317, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3317 = V_CMP_LT_U32_sdwa
19395 { 3333, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3333 = V_CMP_NE_I32_sdwa
19403 { 3341, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3341 = V_CMP_NE_U32_sdwa
19467 { 3405, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3405 = V_CMP_T_I32_sdwa
19475 { 3413, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3413 = V_CMP_T_U32_sdwa
28334 { 12272, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12272 = V_CMPX_EQ_I32_sdwa_gfx9
28335 { 12273, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12273 = V_CMPX_EQ_I32_sdwa_vi
28356 { 12294, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12294 = V_CMPX_EQ_U32_sdwa_gfx9
28357 { 12295, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12295 = V_CMPX_EQ_U32_sdwa_vi
28397 { 12335, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12335 = V_CMPX_F_I32_sdwa_gfx9
28398 { 12336, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12336 = V_CMPX_F_I32_sdwa_vi
28416 { 12354, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12354 = V_CMPX_F_U32_sdwa_gfx9
28417 { 12355, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12355 = V_CMPX_F_U32_sdwa_vi
28460 { 12398, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12398 = V_CMPX_GE_I32_sdwa_gfx9
28461 { 12399, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12399 = V_CMPX_GE_I32_sdwa_vi
28482 { 12420, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12420 = V_CMPX_GE_U32_sdwa_gfx9
28483 { 12421, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12421 = V_CMPX_GE_U32_sdwa_vi
28526 { 12464, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12464 = V_CMPX_GT_I32_sdwa_gfx9
28527 { 12465, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12465 = V_CMPX_GT_I32_sdwa_vi
28548 { 12486, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12486 = V_CMPX_GT_U32_sdwa_gfx9
28549 { 12487, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12487 = V_CMPX_GT_U32_sdwa_vi
28592 { 12530, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12530 = V_CMPX_LE_I32_sdwa_gfx9
28593 { 12531, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12531 = V_CMPX_LE_I32_sdwa_vi
28614 { 12552, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12552 = V_CMPX_LE_U32_sdwa_gfx9
28615 { 12553, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12553 = V_CMPX_LE_U32_sdwa_vi
28680 { 12618, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12618 = V_CMPX_LT_I32_sdwa_gfx9
28681 { 12619, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12619 = V_CMPX_LT_I32_sdwa_vi
28702 { 12640, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12640 = V_CMPX_LT_U32_sdwa_gfx9
28703 { 12641, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12641 = V_CMPX_LT_U32_sdwa_vi
28746 { 12684, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12684 = V_CMPX_NE_I32_sdwa_gfx9
28747 { 12685, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12685 = V_CMPX_NE_I32_sdwa_vi
28768 { 12706, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12706 = V_CMPX_NE_U32_sdwa_gfx9
28769 { 12707, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12707 = V_CMPX_NE_U32_sdwa_vi
28941 { 12879, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12879 = V_CMPX_T_I32_sdwa_gfx9
28942 { 12880, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12880 = V_CMPX_T_I32_sdwa_vi
28960 { 12898, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12898 = V_CMPX_T_U32_sdwa_gfx9
28961 { 12899, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #12899 = V_CMPX_T_U32_sdwa_vi
29047 { 12985, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #12985 = V_CMP_EQ_I32_sdwa_gfx10
29048 { 12986, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #12986 = V_CMP_EQ_I32_sdwa_gfx9
29049 { 12987, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #12987 = V_CMP_EQ_I32_sdwa_vi
29069 { 13007, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13007 = V_CMP_EQ_U32_sdwa_gfx10
29070 { 13008, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13008 = V_CMP_EQ_U32_sdwa_gfx9
29071 { 13009, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13009 = V_CMP_EQ_U32_sdwa_vi
29110 { 13048, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13048 = V_CMP_F_I32_sdwa_gfx10
29111 { 13049, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13049 = V_CMP_F_I32_sdwa_gfx9
29112 { 13050, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13050 = V_CMP_F_I32_sdwa_vi
29129 { 13067, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13067 = V_CMP_F_U32_sdwa_gfx10
29130 { 13068, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13068 = V_CMP_F_U32_sdwa_gfx9
29131 { 13069, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13069 = V_CMP_F_U32_sdwa_vi
29173 { 13111, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13111 = V_CMP_GE_I32_sdwa_gfx10
29174 { 13112, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13112 = V_CMP_GE_I32_sdwa_gfx9
29175 { 13113, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13113 = V_CMP_GE_I32_sdwa_vi
29195 { 13133, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13133 = V_CMP_GE_U32_sdwa_gfx10
29196 { 13134, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13134 = V_CMP_GE_U32_sdwa_gfx9
29197 { 13135, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13135 = V_CMP_GE_U32_sdwa_vi
29239 { 13177, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13177 = V_CMP_GT_I32_sdwa_gfx10
29240 { 13178, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13178 = V_CMP_GT_I32_sdwa_gfx9
29241 { 13179, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13179 = V_CMP_GT_I32_sdwa_vi
29261 { 13199, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13199 = V_CMP_GT_U32_sdwa_gfx10
29262 { 13200, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13200 = V_CMP_GT_U32_sdwa_gfx9
29263 { 13201, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13201 = V_CMP_GT_U32_sdwa_vi
29305 { 13243, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13243 = V_CMP_LE_I32_sdwa_gfx10
29306 { 13244, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13244 = V_CMP_LE_I32_sdwa_gfx9
29307 { 13245, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13245 = V_CMP_LE_I32_sdwa_vi
29327 { 13265, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13265 = V_CMP_LE_U32_sdwa_gfx10
29328 { 13266, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13266 = V_CMP_LE_U32_sdwa_gfx9
29329 { 13267, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13267 = V_CMP_LE_U32_sdwa_vi
29393 { 13331, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13331 = V_CMP_LT_I32_sdwa_gfx10
29394 { 13332, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13332 = V_CMP_LT_I32_sdwa_gfx9
29395 { 13333, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13333 = V_CMP_LT_I32_sdwa_vi
29415 { 13353, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13353 = V_CMP_LT_U32_sdwa_gfx10
29416 { 13354, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13354 = V_CMP_LT_U32_sdwa_gfx9
29417 { 13355, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13355 = V_CMP_LT_U32_sdwa_vi
29459 { 13397, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13397 = V_CMP_NE_I32_sdwa_gfx10
29460 { 13398, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13398 = V_CMP_NE_I32_sdwa_gfx9
29461 { 13399, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13399 = V_CMP_NE_I32_sdwa_vi
29481 { 13419, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13419 = V_CMP_NE_U32_sdwa_gfx10
29482 { 13420, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13420 = V_CMP_NE_U32_sdwa_gfx9
29483 { 13421, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13421 = V_CMP_NE_U32_sdwa_vi
29654 { 13592, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13592 = V_CMP_T_I32_sdwa_gfx10
29655 { 13593, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13593 = V_CMP_T_I32_sdwa_gfx9
29656 { 13594, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13594 = V_CMP_T_I32_sdwa_vi
29673 { 13611, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13611 = V_CMP_T_U32_sdwa_gfx10
29674 { 13612, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13612 = V_CMP_T_U32_sdwa_gfx9
29675 { 13613, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #13613 = V_CMP_T_U32_sdwa_vi