|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18733 { 2671, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2671 = V_CMPX_EQ_I32_e64
18749 { 2687, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2687 = V_CMPX_EQ_U32_e64
18781 { 2719, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2719 = V_CMPX_F_I32_e64
18797 { 2735, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2735 = V_CMPX_F_U32_e64
18829 { 2767, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2767 = V_CMPX_GE_I32_e64
18845 { 2783, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2783 = V_CMPX_GE_U32_e64
18877 { 2815, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2815 = V_CMPX_GT_I32_e64
18893 { 2831, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2831 = V_CMPX_GT_U32_e64
18925 { 2863, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2863 = V_CMPX_LE_I32_e64
18941 { 2879, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2879 = V_CMPX_LE_U32_e64
18989 { 2927, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2927 = V_CMPX_LT_I32_e64
19005 { 2943, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2943 = V_CMPX_LT_U32_e64
19037 { 2975, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2975 = V_CMPX_NE_I32_e64
19053 { 2991, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2991 = V_CMPX_NE_U32_e64
19181 { 3119, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #3119 = V_CMPX_T_I32_e64
19197 { 3135, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #3135 = V_CMPX_T_U32_e64
19242 { 3180, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3180 = V_CMP_EQ_I32_e64
19250 { 3188, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3188 = V_CMP_EQ_U32_e64
19266 { 3204, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3204 = V_CMP_F_I32_e64
19274 { 3212, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3212 = V_CMP_F_U32_e64
19290 { 3228, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3228 = V_CMP_GE_I32_e64
19298 { 3236, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3236 = V_CMP_GE_U32_e64
19314 { 3252, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3252 = V_CMP_GT_I32_e64
19322 { 3260, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3260 = V_CMP_GT_U32_e64
19338 { 3276, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3276 = V_CMP_LE_I32_e64
19346 { 3284, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3284 = V_CMP_LE_U32_e64
19370 { 3308, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3308 = V_CMP_LT_I32_e64
19378 { 3316, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3316 = V_CMP_LT_U32_e64
19394 { 3332, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3332 = V_CMP_NE_I32_e64
19402 { 3340, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3340 = V_CMP_NE_U32_e64
19466 { 3404, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3404 = V_CMP_T_I32_e64
19474 { 3412, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3412 = V_CMP_T_U32_e64
28331 { 12269, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12269 = V_CMPX_EQ_I32_e64_gfx6_gfx7
28332 { 12270, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12270 = V_CMPX_EQ_I32_e64_vi
28353 { 12291, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12291 = V_CMPX_EQ_U32_e64_gfx6_gfx7
28354 { 12292, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12292 = V_CMPX_EQ_U32_e64_vi
28394 { 12332, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12332 = V_CMPX_F_I32_e64_gfx6_gfx7
28395 { 12333, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12333 = V_CMPX_F_I32_e64_vi
28413 { 12351, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12351 = V_CMPX_F_U32_e64_gfx6_gfx7
28414 { 12352, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12352 = V_CMPX_F_U32_e64_vi
28457 { 12395, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12395 = V_CMPX_GE_I32_e64_gfx6_gfx7
28458 { 12396, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12396 = V_CMPX_GE_I32_e64_vi
28479 { 12417, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12417 = V_CMPX_GE_U32_e64_gfx6_gfx7
28480 { 12418, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12418 = V_CMPX_GE_U32_e64_vi
28523 { 12461, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12461 = V_CMPX_GT_I32_e64_gfx6_gfx7
28524 { 12462, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12462 = V_CMPX_GT_I32_e64_vi
28545 { 12483, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12483 = V_CMPX_GT_U32_e64_gfx6_gfx7
28546 { 12484, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12484 = V_CMPX_GT_U32_e64_vi
28589 { 12527, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12527 = V_CMPX_LE_I32_e64_gfx6_gfx7
28590 { 12528, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12528 = V_CMPX_LE_I32_e64_vi
28611 { 12549, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12549 = V_CMPX_LE_U32_e64_gfx6_gfx7
28612 { 12550, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12550 = V_CMPX_LE_U32_e64_vi
28677 { 12615, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12615 = V_CMPX_LT_I32_e64_gfx6_gfx7
28678 { 12616, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12616 = V_CMPX_LT_I32_e64_vi
28699 { 12637, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12637 = V_CMPX_LT_U32_e64_gfx6_gfx7
28700 { 12638, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12638 = V_CMPX_LT_U32_e64_vi
28743 { 12681, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12681 = V_CMPX_NE_I32_e64_gfx6_gfx7
28744 { 12682, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12682 = V_CMPX_NE_I32_e64_vi
28765 { 12703, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12703 = V_CMPX_NE_U32_e64_gfx6_gfx7
28766 { 12704, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12704 = V_CMPX_NE_U32_e64_vi
28938 { 12876, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12876 = V_CMPX_T_I32_e64_gfx6_gfx7
28939 { 12877, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12877 = V_CMPX_T_I32_e64_vi
28957 { 12895, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12895 = V_CMPX_T_U32_e64_gfx6_gfx7
28958 { 12896, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #12896 = V_CMPX_T_U32_e64_vi
29044 { 12982, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #12982 = V_CMP_EQ_I32_e64_gfx10
29045 { 12983, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #12983 = V_CMP_EQ_I32_e64_gfx6_gfx7
29046 { 12984, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #12984 = V_CMP_EQ_I32_e64_vi
29066 { 13004, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13004 = V_CMP_EQ_U32_e64_gfx10
29067 { 13005, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13005 = V_CMP_EQ_U32_e64_gfx6_gfx7
29068 { 13006, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13006 = V_CMP_EQ_U32_e64_vi
29107 { 13045, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13045 = V_CMP_F_I32_e64_gfx10
29108 { 13046, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13046 = V_CMP_F_I32_e64_gfx6_gfx7
29109 { 13047, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13047 = V_CMP_F_I32_e64_vi
29126 { 13064, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13064 = V_CMP_F_U32_e64_gfx10
29127 { 13065, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13065 = V_CMP_F_U32_e64_gfx6_gfx7
29128 { 13066, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13066 = V_CMP_F_U32_e64_vi
29170 { 13108, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13108 = V_CMP_GE_I32_e64_gfx10
29171 { 13109, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13109 = V_CMP_GE_I32_e64_gfx6_gfx7
29172 { 13110, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13110 = V_CMP_GE_I32_e64_vi
29192 { 13130, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13130 = V_CMP_GE_U32_e64_gfx10
29193 { 13131, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13131 = V_CMP_GE_U32_e64_gfx6_gfx7
29194 { 13132, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13132 = V_CMP_GE_U32_e64_vi
29236 { 13174, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13174 = V_CMP_GT_I32_e64_gfx10
29237 { 13175, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13175 = V_CMP_GT_I32_e64_gfx6_gfx7
29238 { 13176, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13176 = V_CMP_GT_I32_e64_vi
29258 { 13196, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13196 = V_CMP_GT_U32_e64_gfx10
29259 { 13197, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13197 = V_CMP_GT_U32_e64_gfx6_gfx7
29260 { 13198, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13198 = V_CMP_GT_U32_e64_vi
29302 { 13240, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13240 = V_CMP_LE_I32_e64_gfx10
29303 { 13241, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13241 = V_CMP_LE_I32_e64_gfx6_gfx7
29304 { 13242, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13242 = V_CMP_LE_I32_e64_vi
29324 { 13262, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13262 = V_CMP_LE_U32_e64_gfx10
29325 { 13263, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13263 = V_CMP_LE_U32_e64_gfx6_gfx7
29326 { 13264, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13264 = V_CMP_LE_U32_e64_vi
29390 { 13328, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13328 = V_CMP_LT_I32_e64_gfx10
29391 { 13329, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13329 = V_CMP_LT_I32_e64_gfx6_gfx7
29392 { 13330, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13330 = V_CMP_LT_I32_e64_vi
29412 { 13350, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13350 = V_CMP_LT_U32_e64_gfx10
29413 { 13351, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13351 = V_CMP_LT_U32_e64_gfx6_gfx7
29414 { 13352, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13352 = V_CMP_LT_U32_e64_vi
29456 { 13394, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13394 = V_CMP_NE_I32_e64_gfx10
29457 { 13395, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13395 = V_CMP_NE_I32_e64_gfx6_gfx7
29458 { 13396, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13396 = V_CMP_NE_I32_e64_vi
29478 { 13416, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13416 = V_CMP_NE_U32_e64_gfx10
29479 { 13417, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13417 = V_CMP_NE_U32_e64_gfx6_gfx7
29480 { 13418, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13418 = V_CMP_NE_U32_e64_vi
29651 { 13589, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13589 = V_CMP_T_I32_e64_gfx10
29652 { 13590, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13590 = V_CMP_T_I32_e64_gfx6_gfx7
29653 { 13591, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13591 = V_CMP_T_I32_e64_vi
29670 { 13608, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13608 = V_CMP_T_U32_e64_gfx10
29671 { 13609, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13609 = V_CMP_T_U32_e64_gfx6_gfx7
29672 { 13610, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #13610 = V_CMP_T_U32_e64_vi