|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18731 { 2669, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2669 = V_CMPX_EQ_I16_sdwa
18747 { 2685, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2685 = V_CMPX_EQ_U16_sdwa
18779 { 2717, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2717 = V_CMPX_F_I16_sdwa
18795 { 2733, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2733 = V_CMPX_F_U16_sdwa
18827 { 2765, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2765 = V_CMPX_GE_I16_sdwa
18843 { 2781, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2781 = V_CMPX_GE_U16_sdwa
18875 { 2813, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2813 = V_CMPX_GT_I16_sdwa
18891 { 2829, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2829 = V_CMPX_GT_U16_sdwa
18923 { 2861, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2861 = V_CMPX_LE_I16_sdwa
18939 { 2877, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2877 = V_CMPX_LE_U16_sdwa
18987 { 2925, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2925 = V_CMPX_LT_I16_sdwa
19003 { 2941, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2941 = V_CMPX_LT_U16_sdwa
19035 { 2973, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2973 = V_CMPX_NE_I16_sdwa
19051 { 2989, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2989 = V_CMPX_NE_U16_sdwa
19179 { 3117, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #3117 = V_CMPX_T_I16_sdwa
19195 { 3133, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #3133 = V_CMPX_T_U16_sdwa
19240 { 3178, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3178 = V_CMP_EQ_I16_sdwa
19248 { 3186, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3186 = V_CMP_EQ_U16_sdwa
19264 { 3202, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3202 = V_CMP_F_I16_sdwa
19272 { 3210, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3210 = V_CMP_F_U16_sdwa
19288 { 3226, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3226 = V_CMP_GE_I16_sdwa
19296 { 3234, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3234 = V_CMP_GE_U16_sdwa
19312 { 3250, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3250 = V_CMP_GT_I16_sdwa
19320 { 3258, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3258 = V_CMP_GT_U16_sdwa
19336 { 3274, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3274 = V_CMP_LE_I16_sdwa
19344 { 3282, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3282 = V_CMP_LE_U16_sdwa
19368 { 3306, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3306 = V_CMP_LT_I16_sdwa
19376 { 3314, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3314 = V_CMP_LT_U16_sdwa
19392 { 3330, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3330 = V_CMP_NE_I16_sdwa
19400 { 3338, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3338 = V_CMP_NE_U16_sdwa
19464 { 3402, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3402 = V_CMP_T_I16_sdwa
19472 { 3410, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3410 = V_CMP_T_U16_sdwa
28325 { 12263, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12263 = V_CMPX_EQ_I16_sdwa_gfx9
28326 { 12264, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12264 = V_CMPX_EQ_I16_sdwa_vi
28347 { 12285, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12285 = V_CMPX_EQ_U16_sdwa_gfx9
28348 { 12286, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12286 = V_CMPX_EQ_U16_sdwa_vi
28388 { 12326, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12326 = V_CMPX_F_I16_sdwa_gfx9
28389 { 12327, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12327 = V_CMPX_F_I16_sdwa_vi
28407 { 12345, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12345 = V_CMPX_F_U16_sdwa_gfx9
28408 { 12346, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12346 = V_CMPX_F_U16_sdwa_vi
28451 { 12389, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12389 = V_CMPX_GE_I16_sdwa_gfx9
28452 { 12390, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12390 = V_CMPX_GE_I16_sdwa_vi
28473 { 12411, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12411 = V_CMPX_GE_U16_sdwa_gfx9
28474 { 12412, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12412 = V_CMPX_GE_U16_sdwa_vi
28517 { 12455, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12455 = V_CMPX_GT_I16_sdwa_gfx9
28518 { 12456, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12456 = V_CMPX_GT_I16_sdwa_vi
28539 { 12477, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12477 = V_CMPX_GT_U16_sdwa_gfx9
28540 { 12478, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12478 = V_CMPX_GT_U16_sdwa_vi
28583 { 12521, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12521 = V_CMPX_LE_I16_sdwa_gfx9
28584 { 12522, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12522 = V_CMPX_LE_I16_sdwa_vi
28605 { 12543, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12543 = V_CMPX_LE_U16_sdwa_gfx9
28606 { 12544, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12544 = V_CMPX_LE_U16_sdwa_vi
28671 { 12609, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12609 = V_CMPX_LT_I16_sdwa_gfx9
28672 { 12610, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12610 = V_CMPX_LT_I16_sdwa_vi
28693 { 12631, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12631 = V_CMPX_LT_U16_sdwa_gfx9
28694 { 12632, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12632 = V_CMPX_LT_U16_sdwa_vi
28737 { 12675, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12675 = V_CMPX_NE_I16_sdwa_gfx9
28738 { 12676, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12676 = V_CMPX_NE_I16_sdwa_vi
28759 { 12697, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12697 = V_CMPX_NE_U16_sdwa_gfx9
28760 { 12698, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12698 = V_CMPX_NE_U16_sdwa_vi
28932 { 12870, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12870 = V_CMPX_T_I16_sdwa_gfx9
28933 { 12871, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12871 = V_CMPX_T_I16_sdwa_vi
28951 { 12889, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12889 = V_CMPX_T_U16_sdwa_gfx9
28952 { 12890, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #12890 = V_CMPX_T_U16_sdwa_vi
29038 { 12976, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #12976 = V_CMP_EQ_I16_sdwa_gfx10
29039 { 12977, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #12977 = V_CMP_EQ_I16_sdwa_gfx9
29040 { 12978, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #12978 = V_CMP_EQ_I16_sdwa_vi
29060 { 12998, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #12998 = V_CMP_EQ_U16_sdwa_gfx10
29061 { 12999, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #12999 = V_CMP_EQ_U16_sdwa_gfx9
29062 { 13000, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13000 = V_CMP_EQ_U16_sdwa_vi
29102 { 13040, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13040 = V_CMP_F_I16_sdwa_gfx9
29103 { 13041, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13041 = V_CMP_F_I16_sdwa_vi
29121 { 13059, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13059 = V_CMP_F_U16_sdwa_gfx9
29122 { 13060, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13060 = V_CMP_F_U16_sdwa_vi
29164 { 13102, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13102 = V_CMP_GE_I16_sdwa_gfx10
29165 { 13103, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13103 = V_CMP_GE_I16_sdwa_gfx9
29166 { 13104, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13104 = V_CMP_GE_I16_sdwa_vi
29186 { 13124, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13124 = V_CMP_GE_U16_sdwa_gfx10
29187 { 13125, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13125 = V_CMP_GE_U16_sdwa_gfx9
29188 { 13126, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13126 = V_CMP_GE_U16_sdwa_vi
29230 { 13168, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13168 = V_CMP_GT_I16_sdwa_gfx10
29231 { 13169, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13169 = V_CMP_GT_I16_sdwa_gfx9
29232 { 13170, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13170 = V_CMP_GT_I16_sdwa_vi
29252 { 13190, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13190 = V_CMP_GT_U16_sdwa_gfx10
29253 { 13191, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13191 = V_CMP_GT_U16_sdwa_gfx9
29254 { 13192, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13192 = V_CMP_GT_U16_sdwa_vi
29296 { 13234, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13234 = V_CMP_LE_I16_sdwa_gfx10
29297 { 13235, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13235 = V_CMP_LE_I16_sdwa_gfx9
29298 { 13236, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13236 = V_CMP_LE_I16_sdwa_vi
29318 { 13256, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13256 = V_CMP_LE_U16_sdwa_gfx10
29319 { 13257, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13257 = V_CMP_LE_U16_sdwa_gfx9
29320 { 13258, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13258 = V_CMP_LE_U16_sdwa_vi
29384 { 13322, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13322 = V_CMP_LT_I16_sdwa_gfx10
29385 { 13323, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13323 = V_CMP_LT_I16_sdwa_gfx9
29386 { 13324, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13324 = V_CMP_LT_I16_sdwa_vi
29406 { 13344, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13344 = V_CMP_LT_U16_sdwa_gfx10
29407 { 13345, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13345 = V_CMP_LT_U16_sdwa_gfx9
29408 { 13346, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13346 = V_CMP_LT_U16_sdwa_vi
29450 { 13388, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13388 = V_CMP_NE_I16_sdwa_gfx10
29451 { 13389, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13389 = V_CMP_NE_I16_sdwa_gfx9
29452 { 13390, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13390 = V_CMP_NE_I16_sdwa_vi
29472 { 13410, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13410 = V_CMP_NE_U16_sdwa_gfx10
29473 { 13411, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13411 = V_CMP_NE_U16_sdwa_gfx9
29474 { 13412, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13412 = V_CMP_NE_U16_sdwa_vi
29646 { 13584, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13584 = V_CMP_T_I16_sdwa_gfx9
29647 { 13585, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13585 = V_CMP_T_I16_sdwa_vi
29665 { 13603, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13603 = V_CMP_T_U16_sdwa_gfx9
29666 { 13604, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #13604 = V_CMP_T_U16_sdwa_vi