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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18730 { 2668, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2668 = V_CMPX_EQ_I16_nosdst_sdwa
18746 { 2684, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2684 = V_CMPX_EQ_U16_nosdst_sdwa
18778 { 2716, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2716 = V_CMPX_F_I16_nosdst_sdwa
18794 { 2732, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2732 = V_CMPX_F_U16_nosdst_sdwa
18826 { 2764, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2764 = V_CMPX_GE_I16_nosdst_sdwa
18842 { 2780, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2780 = V_CMPX_GE_U16_nosdst_sdwa
18874 { 2812, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2812 = V_CMPX_GT_I16_nosdst_sdwa
18890 { 2828, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2828 = V_CMPX_GT_U16_nosdst_sdwa
18922 { 2860, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2860 = V_CMPX_LE_I16_nosdst_sdwa
18938 { 2876, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2876 = V_CMPX_LE_U16_nosdst_sdwa
18986 { 2924, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2924 = V_CMPX_LT_I16_nosdst_sdwa
19002 { 2940, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2940 = V_CMPX_LT_U16_nosdst_sdwa
19034 { 2972, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2972 = V_CMPX_NE_I16_nosdst_sdwa
19050 { 2988, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2988 = V_CMPX_NE_U16_nosdst_sdwa
19178 { 3116, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #3116 = V_CMPX_T_I16_nosdst_sdwa
19194 { 3132, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #3132 = V_CMPX_T_U16_nosdst_sdwa
28324 { 12262, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12262 = V_CMPX_EQ_I16_sdwa_gfx10
28346 { 12284, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12284 = V_CMPX_EQ_U16_sdwa_gfx10
28450 { 12388, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12388 = V_CMPX_GE_I16_sdwa_gfx10
28472 { 12410, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12410 = V_CMPX_GE_U16_sdwa_gfx10
28516 { 12454, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12454 = V_CMPX_GT_I16_sdwa_gfx10
28538 { 12476, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12476 = V_CMPX_GT_U16_sdwa_gfx10
28582 { 12520, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12520 = V_CMPX_LE_I16_sdwa_gfx10
28604 { 12542, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12542 = V_CMPX_LE_U16_sdwa_gfx10
28670 { 12608, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12608 = V_CMPX_LT_I16_sdwa_gfx10
28692 { 12630, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12630 = V_CMPX_LT_U16_sdwa_gfx10
28736 { 12674, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12674 = V_CMPX_NE_I16_sdwa_gfx10
28758 { 12696, 6, 0, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #12696 = V_CMPX_NE_U16_sdwa_gfx10