|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18699 { 2637, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2637 = V_CMPX_CLASS_F16_sdwa
18715 { 2653, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2653 = V_CMPX_EQ_F16_sdwa
18763 { 2701, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2701 = V_CMPX_F_F16_sdwa
18811 { 2749, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2749 = V_CMPX_GE_F16_sdwa
18859 { 2797, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2797 = V_CMPX_GT_F16_sdwa
18907 { 2845, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2845 = V_CMPX_LE_F16_sdwa
18955 { 2893, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2893 = V_CMPX_LG_F16_sdwa
18971 { 2909, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2909 = V_CMPX_LT_F16_sdwa
19019 { 2957, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2957 = V_CMPX_NEQ_F16_sdwa
19067 { 3005, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3005 = V_CMPX_NGE_F16_sdwa
19083 { 3021, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3021 = V_CMPX_NGT_F16_sdwa
19099 { 3037, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3037 = V_CMPX_NLE_F16_sdwa
19115 { 3053, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3053 = V_CMPX_NLG_F16_sdwa
19131 { 3069, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3069 = V_CMPX_NLT_F16_sdwa
19147 { 3085, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3085 = V_CMPX_O_F16_sdwa
19163 { 3101, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3101 = V_CMPX_TRU_F16_sdwa
19211 { 3149, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3149 = V_CMPX_U_F16_sdwa
19224 { 3162, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3162 = V_CMP_CLASS_F16_sdwa
19232 { 3170, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3170 = V_CMP_EQ_F16_sdwa
19256 { 3194, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3194 = V_CMP_F_F16_sdwa
19280 { 3218, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3218 = V_CMP_GE_F16_sdwa
19304 { 3242, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3242 = V_CMP_GT_F16_sdwa
19328 { 3266, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3266 = V_CMP_LE_F16_sdwa
19352 { 3290, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3290 = V_CMP_LG_F16_sdwa
19360 { 3298, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3298 = V_CMP_LT_F16_sdwa
19384 { 3322, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3322 = V_CMP_NEQ_F16_sdwa
19408 { 3346, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3346 = V_CMP_NGE_F16_sdwa
19416 { 3354, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3354 = V_CMP_NGT_F16_sdwa
19424 { 3362, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3362 = V_CMP_NLE_F16_sdwa
19432 { 3370, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3370 = V_CMP_NLG_F16_sdwa
19440 { 3378, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3378 = V_CMP_NLT_F16_sdwa
19448 { 3386, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3386 = V_CMP_O_F16_sdwa
19456 { 3394, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3394 = V_CMP_TRU_F16_sdwa
19480 { 3418, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3418 = V_CMP_U_F16_sdwa
28281 { 12219, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12219 = V_CMPX_CLASS_F16_sdwa_gfx9
28282 { 12220, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12220 = V_CMPX_CLASS_F16_sdwa_vi
28303 { 12241, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12241 = V_CMPX_EQ_F16_sdwa_gfx9
28304 { 12242, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12242 = V_CMPX_EQ_F16_sdwa_vi
28369 { 12307, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12307 = V_CMPX_F_F16_sdwa_gfx9
28370 { 12308, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12308 = V_CMPX_F_F16_sdwa_vi
28429 { 12367, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12367 = V_CMPX_GE_F16_sdwa_gfx9
28430 { 12368, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12368 = V_CMPX_GE_F16_sdwa_vi
28495 { 12433, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12433 = V_CMPX_GT_F16_sdwa_gfx9
28496 { 12434, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12434 = V_CMPX_GT_F16_sdwa_vi
28561 { 12499, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12499 = V_CMPX_LE_F16_sdwa_gfx9
28562 { 12500, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12500 = V_CMPX_LE_F16_sdwa_vi
28627 { 12565, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12565 = V_CMPX_LG_F16_sdwa_gfx9
28628 { 12566, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12566 = V_CMPX_LG_F16_sdwa_vi
28649 { 12587, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12587 = V_CMPX_LT_F16_sdwa_gfx9
28650 { 12588, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12588 = V_CMPX_LT_F16_sdwa_vi
28715 { 12653, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12653 = V_CMPX_NEQ_F16_sdwa_gfx9
28716 { 12654, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12654 = V_CMPX_NEQ_F16_sdwa_vi
28781 { 12719, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12719 = V_CMPX_NGE_F16_sdwa_gfx9
28782 { 12720, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12720 = V_CMPX_NGE_F16_sdwa_vi
28803 { 12741, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12741 = V_CMPX_NGT_F16_sdwa_gfx9
28804 { 12742, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12742 = V_CMPX_NGT_F16_sdwa_vi
28825 { 12763, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12763 = V_CMPX_NLE_F16_sdwa_gfx9
28826 { 12764, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12764 = V_CMPX_NLE_F16_sdwa_vi
28847 { 12785, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12785 = V_CMPX_NLG_F16_sdwa_gfx9
28848 { 12786, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12786 = V_CMPX_NLG_F16_sdwa_vi
28869 { 12807, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12807 = V_CMPX_NLT_F16_sdwa_gfx9
28870 { 12808, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12808 = V_CMPX_NLT_F16_sdwa_vi
28891 { 12829, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12829 = V_CMPX_O_F16_sdwa_gfx9
28892 { 12830, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12830 = V_CMPX_O_F16_sdwa_vi
28913 { 12851, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12851 = V_CMPX_TRU_F16_sdwa_gfx9
28914 { 12852, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12852 = V_CMPX_TRU_F16_sdwa_vi
28973 { 12911, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12911 = V_CMPX_U_F16_sdwa_gfx9
28974 { 12912, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #12912 = V_CMPX_U_F16_sdwa_vi
28994 { 12932, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #12932 = V_CMP_CLASS_F16_sdwa_gfx10
28995 { 12933, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #12933 = V_CMP_CLASS_F16_sdwa_gfx9
28996 { 12934, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #12934 = V_CMP_CLASS_F16_sdwa_vi
29016 { 12954, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #12954 = V_CMP_EQ_F16_sdwa_gfx10
29017 { 12955, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #12955 = V_CMP_EQ_F16_sdwa_gfx9
29018 { 12956, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #12956 = V_CMP_EQ_F16_sdwa_vi
29082 { 13020, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13020 = V_CMP_F_F16_sdwa_gfx10
29083 { 13021, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13021 = V_CMP_F_F16_sdwa_gfx9
29084 { 13022, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13022 = V_CMP_F_F16_sdwa_vi
29142 { 13080, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13080 = V_CMP_GE_F16_sdwa_gfx10
29143 { 13081, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13081 = V_CMP_GE_F16_sdwa_gfx9
29144 { 13082, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13082 = V_CMP_GE_F16_sdwa_vi
29208 { 13146, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13146 = V_CMP_GT_F16_sdwa_gfx10
29209 { 13147, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13147 = V_CMP_GT_F16_sdwa_gfx9
29210 { 13148, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13148 = V_CMP_GT_F16_sdwa_vi
29274 { 13212, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13212 = V_CMP_LE_F16_sdwa_gfx10
29275 { 13213, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13213 = V_CMP_LE_F16_sdwa_gfx9
29276 { 13214, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13214 = V_CMP_LE_F16_sdwa_vi
29340 { 13278, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13278 = V_CMP_LG_F16_sdwa_gfx10
29341 { 13279, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13279 = V_CMP_LG_F16_sdwa_gfx9
29342 { 13280, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13280 = V_CMP_LG_F16_sdwa_vi
29362 { 13300, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13300 = V_CMP_LT_F16_sdwa_gfx10
29363 { 13301, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13301 = V_CMP_LT_F16_sdwa_gfx9
29364 { 13302, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13302 = V_CMP_LT_F16_sdwa_vi
29428 { 13366, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13366 = V_CMP_NEQ_F16_sdwa_gfx10
29429 { 13367, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13367 = V_CMP_NEQ_F16_sdwa_gfx9
29430 { 13368, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13368 = V_CMP_NEQ_F16_sdwa_vi
29494 { 13432, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13432 = V_CMP_NGE_F16_sdwa_gfx10
29495 { 13433, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13433 = V_CMP_NGE_F16_sdwa_gfx9
29496 { 13434, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13434 = V_CMP_NGE_F16_sdwa_vi
29516 { 13454, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13454 = V_CMP_NGT_F16_sdwa_gfx10
29517 { 13455, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13455 = V_CMP_NGT_F16_sdwa_gfx9
29518 { 13456, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13456 = V_CMP_NGT_F16_sdwa_vi
29538 { 13476, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13476 = V_CMP_NLE_F16_sdwa_gfx10
29539 { 13477, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13477 = V_CMP_NLE_F16_sdwa_gfx9
29540 { 13478, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13478 = V_CMP_NLE_F16_sdwa_vi
29560 { 13498, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13498 = V_CMP_NLG_F16_sdwa_gfx10
29561 { 13499, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13499 = V_CMP_NLG_F16_sdwa_gfx9
29562 { 13500, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13500 = V_CMP_NLG_F16_sdwa_vi
29582 { 13520, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13520 = V_CMP_NLT_F16_sdwa_gfx10
29583 { 13521, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13521 = V_CMP_NLT_F16_sdwa_gfx9
29584 { 13522, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13522 = V_CMP_NLT_F16_sdwa_vi
29604 { 13542, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13542 = V_CMP_O_F16_sdwa_gfx10
29605 { 13543, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13543 = V_CMP_O_F16_sdwa_gfx9
29606 { 13544, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13544 = V_CMP_O_F16_sdwa_vi
29626 { 13564, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13564 = V_CMP_TRU_F16_sdwa_gfx10
29627 { 13565, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13565 = V_CMP_TRU_F16_sdwa_gfx9
29628 { 13566, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13566 = V_CMP_TRU_F16_sdwa_vi
29686 { 13624, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13624 = V_CMP_U_F16_sdwa_gfx10
29687 { 13625, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13625 = V_CMP_U_F16_sdwa_gfx9
29688 { 13626, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #13626 = V_CMP_U_F16_sdwa_vi