|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18694 { 2632, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2632 = V_CMPX_CLASS_F16_e32
18696 { 2634, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2634 = V_CMPX_CLASS_F16_nosdst_e32
18710 { 2648, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2648 = V_CMPX_EQ_F16_e32
18712 { 2650, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2650 = V_CMPX_EQ_F16_nosdst_e32
18758 { 2696, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2696 = V_CMPX_F_F16_e32
18760 { 2698, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2698 = V_CMPX_F_F16_nosdst_e32
18806 { 2744, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2744 = V_CMPX_GE_F16_e32
18808 { 2746, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2746 = V_CMPX_GE_F16_nosdst_e32
18854 { 2792, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2792 = V_CMPX_GT_F16_e32
18856 { 2794, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2794 = V_CMPX_GT_F16_nosdst_e32
18902 { 2840, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2840 = V_CMPX_LE_F16_e32
18904 { 2842, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2842 = V_CMPX_LE_F16_nosdst_e32
18950 { 2888, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2888 = V_CMPX_LG_F16_e32
18952 { 2890, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2890 = V_CMPX_LG_F16_nosdst_e32
18966 { 2904, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2904 = V_CMPX_LT_F16_e32
18968 { 2906, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2906 = V_CMPX_LT_F16_nosdst_e32
19014 { 2952, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2952 = V_CMPX_NEQ_F16_e32
19016 { 2954, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2954 = V_CMPX_NEQ_F16_nosdst_e32
19062 { 3000, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3000 = V_CMPX_NGE_F16_e32
19064 { 3002, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3002 = V_CMPX_NGE_F16_nosdst_e32
19078 { 3016, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3016 = V_CMPX_NGT_F16_e32
19080 { 3018, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3018 = V_CMPX_NGT_F16_nosdst_e32
19094 { 3032, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3032 = V_CMPX_NLE_F16_e32
19096 { 3034, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3034 = V_CMPX_NLE_F16_nosdst_e32
19110 { 3048, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3048 = V_CMPX_NLG_F16_e32
19112 { 3050, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3050 = V_CMPX_NLG_F16_nosdst_e32
19126 { 3064, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3064 = V_CMPX_NLT_F16_e32
19128 { 3066, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3066 = V_CMPX_NLT_F16_nosdst_e32
19142 { 3080, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3080 = V_CMPX_O_F16_e32
19144 { 3082, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3082 = V_CMPX_O_F16_nosdst_e32
19158 { 3096, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3096 = V_CMPX_TRU_F16_e32
19160 { 3098, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3098 = V_CMPX_TRU_F16_nosdst_e32
19206 { 3144, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3144 = V_CMPX_U_F16_e32
19208 { 3146, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3146 = V_CMPX_U_F16_nosdst_e32
19222 { 3160, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3160 = V_CMP_CLASS_F16_e32
19230 { 3168, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3168 = V_CMP_EQ_F16_e32
19254 { 3192, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3192 = V_CMP_F_F16_e32
19278 { 3216, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3216 = V_CMP_GE_F16_e32
19302 { 3240, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3240 = V_CMP_GT_F16_e32
19326 { 3264, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3264 = V_CMP_LE_F16_e32
19350 { 3288, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3288 = V_CMP_LG_F16_e32
19358 { 3296, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3296 = V_CMP_LT_F16_e32
19382 { 3320, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3320 = V_CMP_NEQ_F16_e32
19406 { 3344, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3344 = V_CMP_NGE_F16_e32
19414 { 3352, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3352 = V_CMP_NGT_F16_e32
19422 { 3360, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3360 = V_CMP_NLE_F16_e32
19430 { 3368, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3368 = V_CMP_NLG_F16_e32
19438 { 3376, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3376 = V_CMP_NLT_F16_e32
19446 { 3384, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3384 = V_CMP_O_F16_e32
19454 { 3392, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3392 = V_CMP_TRU_F16_e32
19478 { 3416, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3416 = V_CMP_U_F16_e32
28276 { 12214, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12214 = V_CMPX_CLASS_F16_e32_gfx10
28277 { 12215, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12215 = V_CMPX_CLASS_F16_e32_vi
28298 { 12236, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12236 = V_CMPX_EQ_F16_e32_gfx10
28299 { 12237, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12237 = V_CMPX_EQ_F16_e32_vi
28364 { 12302, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12302 = V_CMPX_F_F16_e32_gfx10
28365 { 12303, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12303 = V_CMPX_F_F16_e32_vi
28424 { 12362, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12362 = V_CMPX_GE_F16_e32_gfx10
28425 { 12363, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12363 = V_CMPX_GE_F16_e32_vi
28490 { 12428, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12428 = V_CMPX_GT_F16_e32_gfx10
28491 { 12429, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12429 = V_CMPX_GT_F16_e32_vi
28556 { 12494, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12494 = V_CMPX_LE_F16_e32_gfx10
28557 { 12495, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12495 = V_CMPX_LE_F16_e32_vi
28622 { 12560, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12560 = V_CMPX_LG_F16_e32_gfx10
28623 { 12561, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12561 = V_CMPX_LG_F16_e32_vi
28644 { 12582, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12582 = V_CMPX_LT_F16_e32_gfx10
28645 { 12583, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12583 = V_CMPX_LT_F16_e32_vi
28710 { 12648, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12648 = V_CMPX_NEQ_F16_e32_gfx10
28711 { 12649, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12649 = V_CMPX_NEQ_F16_e32_vi
28776 { 12714, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12714 = V_CMPX_NGE_F16_e32_gfx10
28777 { 12715, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12715 = V_CMPX_NGE_F16_e32_vi
28798 { 12736, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12736 = V_CMPX_NGT_F16_e32_gfx10
28799 { 12737, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12737 = V_CMPX_NGT_F16_e32_vi
28820 { 12758, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12758 = V_CMPX_NLE_F16_e32_gfx10
28821 { 12759, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12759 = V_CMPX_NLE_F16_e32_vi
28842 { 12780, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12780 = V_CMPX_NLG_F16_e32_gfx10
28843 { 12781, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12781 = V_CMPX_NLG_F16_e32_vi
28864 { 12802, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12802 = V_CMPX_NLT_F16_e32_gfx10
28865 { 12803, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12803 = V_CMPX_NLT_F16_e32_vi
28886 { 12824, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12824 = V_CMPX_O_F16_e32_gfx10
28887 { 12825, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12825 = V_CMPX_O_F16_e32_vi
28908 { 12846, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12846 = V_CMPX_TRU_F16_e32_gfx10
28909 { 12847, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12847 = V_CMPX_TRU_F16_e32_vi
28968 { 12906, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #12906 = V_CMPX_U_F16_e32_gfx10
28969 { 12907, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #12907 = V_CMPX_U_F16_e32_vi
28990 { 12928, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #12928 = V_CMP_CLASS_F16_e32_gfx10
28991 { 12929, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #12929 = V_CMP_CLASS_F16_e32_vi
29012 { 12950, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #12950 = V_CMP_EQ_F16_e32_gfx10
29013 { 12951, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #12951 = V_CMP_EQ_F16_e32_vi
29078 { 13016, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13016 = V_CMP_F_F16_e32_gfx10
29079 { 13017, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13017 = V_CMP_F_F16_e32_vi
29138 { 13076, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13076 = V_CMP_GE_F16_e32_gfx10
29139 { 13077, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13077 = V_CMP_GE_F16_e32_vi
29204 { 13142, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13142 = V_CMP_GT_F16_e32_gfx10
29205 { 13143, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13143 = V_CMP_GT_F16_e32_vi
29270 { 13208, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13208 = V_CMP_LE_F16_e32_gfx10
29271 { 13209, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13209 = V_CMP_LE_F16_e32_vi
29336 { 13274, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13274 = V_CMP_LG_F16_e32_gfx10
29337 { 13275, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13275 = V_CMP_LG_F16_e32_vi
29358 { 13296, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13296 = V_CMP_LT_F16_e32_gfx10
29359 { 13297, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13297 = V_CMP_LT_F16_e32_vi
29424 { 13362, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13362 = V_CMP_NEQ_F16_e32_gfx10
29425 { 13363, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13363 = V_CMP_NEQ_F16_e32_vi
29490 { 13428, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13428 = V_CMP_NGE_F16_e32_gfx10
29491 { 13429, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13429 = V_CMP_NGE_F16_e32_vi
29512 { 13450, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13450 = V_CMP_NGT_F16_e32_gfx10
29513 { 13451, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13451 = V_CMP_NGT_F16_e32_vi
29534 { 13472, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13472 = V_CMP_NLE_F16_e32_gfx10
29535 { 13473, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13473 = V_CMP_NLE_F16_e32_vi
29556 { 13494, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13494 = V_CMP_NLG_F16_e32_gfx10
29557 { 13495, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13495 = V_CMP_NLG_F16_e32_vi
29578 { 13516, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13516 = V_CMP_NLT_F16_e32_gfx10
29579 { 13517, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13517 = V_CMP_NLT_F16_e32_vi
29600 { 13538, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13538 = V_CMP_O_F16_e32_gfx10
29601 { 13539, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13539 = V_CMP_O_F16_e32_vi
29622 { 13560, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13560 = V_CMP_TRU_F16_e32_gfx10
29623 { 13561, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13561 = V_CMP_TRU_F16_e32_vi
29682 { 13620, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13620 = V_CMP_U_F16_e32_gfx10
29683 { 13621, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #13621 = V_CMP_U_F16_e32_vi