|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18460 { 2398, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2398 = V_CMPSX_EQ_F64_e32
18462 { 2400, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2400 = V_CMPSX_EQ_F64_nosdst_e32
18470 { 2408, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2408 = V_CMPSX_F_F64_e32
18472 { 2410, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2410 = V_CMPSX_F_F64_nosdst_e32
18480 { 2418, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2418 = V_CMPSX_GE_F64_e32
18482 { 2420, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2420 = V_CMPSX_GE_F64_nosdst_e32
18490 { 2428, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2428 = V_CMPSX_GT_F64_e32
18492 { 2430, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2430 = V_CMPSX_GT_F64_nosdst_e32
18500 { 2438, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2438 = V_CMPSX_LE_F64_e32
18502 { 2440, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2440 = V_CMPSX_LE_F64_nosdst_e32
18510 { 2448, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2448 = V_CMPSX_LG_F64_e32
18512 { 2450, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2450 = V_CMPSX_LG_F64_nosdst_e32
18520 { 2458, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2458 = V_CMPSX_LT_F64_e32
18522 { 2460, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2460 = V_CMPSX_LT_F64_nosdst_e32
18530 { 2468, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2468 = V_CMPSX_NEQ_F64_e32
18532 { 2470, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2470 = V_CMPSX_NEQ_F64_nosdst_e32
18540 { 2478, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2478 = V_CMPSX_NGE_F64_e32
18542 { 2480, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2480 = V_CMPSX_NGE_F64_nosdst_e32
18550 { 2488, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2488 = V_CMPSX_NGT_F64_e32
18552 { 2490, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2490 = V_CMPSX_NGT_F64_nosdst_e32
18560 { 2498, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2498 = V_CMPSX_NLE_F64_e32
18562 { 2500, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2500 = V_CMPSX_NLE_F64_nosdst_e32
18570 { 2508, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2508 = V_CMPSX_NLG_F64_e32
18572 { 2510, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2510 = V_CMPSX_NLG_F64_nosdst_e32
18580 { 2518, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2518 = V_CMPSX_NLT_F64_e32
18582 { 2520, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2520 = V_CMPSX_NLT_F64_nosdst_e32
18590 { 2528, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2528 = V_CMPSX_O_F64_e32
18592 { 2530, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2530 = V_CMPSX_O_F64_nosdst_e32
18600 { 2538, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2538 = V_CMPSX_TRU_F64_e32
18602 { 2540, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2540 = V_CMPSX_TRU_F64_nosdst_e32
18610 { 2548, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2548 = V_CMPSX_U_F64_e32
18612 { 2550, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2550 = V_CMPSX_U_F64_nosdst_e32
18617 { 2555, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2555 = V_CMPS_EQ_F64_e32
18622 { 2560, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2560 = V_CMPS_F_F64_e32
18627 { 2565, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2565 = V_CMPS_GE_F64_e32
18632 { 2570, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2570 = V_CMPS_GT_F64_e32
18637 { 2575, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2575 = V_CMPS_LE_F64_e32
18642 { 2580, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2580 = V_CMPS_LG_F64_e32
18647 { 2585, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2585 = V_CMPS_LT_F64_e32
18652 { 2590, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2590 = V_CMPS_NEQ_F64_e32
18657 { 2595, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2595 = V_CMPS_NGE_F64_e32
18662 { 2600, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2600 = V_CMPS_NGT_F64_e32
18667 { 2605, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2605 = V_CMPS_NLE_F64_e32
18672 { 2610, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2610 = V_CMPS_NLG_F64_e32
18677 { 2615, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2615 = V_CMPS_NLT_F64_e32
18682 { 2620, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2620 = V_CMPS_O_F64_e32
18687 { 2625, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2625 = V_CMPS_TRU_F64_e32
18692 { 2630, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2630 = V_CMPS_U_F64_e32
18722 { 2660, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2660 = V_CMPX_EQ_F64_e32
18724 { 2662, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2662 = V_CMPX_EQ_F64_nosdst_e32
18770 { 2708, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2708 = V_CMPX_F_F64_e32
18772 { 2710, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2710 = V_CMPX_F_F64_nosdst_e32
18818 { 2756, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2756 = V_CMPX_GE_F64_e32
18820 { 2758, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2758 = V_CMPX_GE_F64_nosdst_e32
18866 { 2804, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2804 = V_CMPX_GT_F64_e32
18868 { 2806, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2806 = V_CMPX_GT_F64_nosdst_e32
18914 { 2852, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2852 = V_CMPX_LE_F64_e32
18916 { 2854, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2854 = V_CMPX_LE_F64_nosdst_e32
18962 { 2900, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2900 = V_CMPX_LG_F64_e32
18964 { 2902, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2902 = V_CMPX_LG_F64_nosdst_e32
18978 { 2916, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2916 = V_CMPX_LT_F64_e32
18980 { 2918, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2918 = V_CMPX_LT_F64_nosdst_e32
19026 { 2964, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2964 = V_CMPX_NEQ_F64_e32
19028 { 2966, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2966 = V_CMPX_NEQ_F64_nosdst_e32
19074 { 3012, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3012 = V_CMPX_NGE_F64_e32
19076 { 3014, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3014 = V_CMPX_NGE_F64_nosdst_e32
19090 { 3028, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3028 = V_CMPX_NGT_F64_e32
19092 { 3030, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3030 = V_CMPX_NGT_F64_nosdst_e32
19106 { 3044, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3044 = V_CMPX_NLE_F64_e32
19108 { 3046, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3046 = V_CMPX_NLE_F64_nosdst_e32
19122 { 3060, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3060 = V_CMPX_NLG_F64_e32
19124 { 3062, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3062 = V_CMPX_NLG_F64_nosdst_e32
19138 { 3076, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3076 = V_CMPX_NLT_F64_e32
19140 { 3078, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3078 = V_CMPX_NLT_F64_nosdst_e32
19154 { 3092, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3092 = V_CMPX_O_F64_e32
19156 { 3094, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3094 = V_CMPX_O_F64_nosdst_e32
19170 { 3108, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3108 = V_CMPX_TRU_F64_e32
19172 { 3110, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3110 = V_CMPX_TRU_F64_nosdst_e32
19218 { 3156, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3156 = V_CMPX_U_F64_e32
19220 { 3158, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3158 = V_CMPX_U_F64_nosdst_e32
19236 { 3174, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3174 = V_CMP_EQ_F64_e32
19260 { 3198, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3198 = V_CMP_F_F64_e32
19284 { 3222, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3222 = V_CMP_GE_F64_e32
19308 { 3246, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3246 = V_CMP_GT_F64_e32
19332 { 3270, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3270 = V_CMP_LE_F64_e32
19356 { 3294, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3294 = V_CMP_LG_F64_e32
19364 { 3302, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3302 = V_CMP_LT_F64_e32
19388 { 3326, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3326 = V_CMP_NEQ_F64_e32
19412 { 3350, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3350 = V_CMP_NGE_F64_e32
19420 { 3358, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3358 = V_CMP_NGT_F64_e32
19428 { 3366, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3366 = V_CMP_NLE_F64_e32
19436 { 3374, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3374 = V_CMP_NLG_F64_e32
19444 { 3382, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3382 = V_CMP_NLT_F64_e32
19452 { 3390, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3390 = V_CMP_O_F64_e32
19460 { 3398, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3398 = V_CMP_TRU_F64_e32
19484 { 3422, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3422 = V_CMP_U_F64_e32
28150 { 12088, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12088 = V_CMPSX_EQ_F64_e32_gfx6_gfx7
28154 { 12092, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12092 = V_CMPSX_F_F64_e32_gfx6_gfx7
28158 { 12096, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12096 = V_CMPSX_GE_F64_e32_gfx6_gfx7
28162 { 12100, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12100 = V_CMPSX_GT_F64_e32_gfx6_gfx7
28166 { 12104, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12104 = V_CMPSX_LE_F64_e32_gfx6_gfx7
28170 { 12108, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12108 = V_CMPSX_LG_F64_e32_gfx6_gfx7
28174 { 12112, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12112 = V_CMPSX_LT_F64_e32_gfx6_gfx7
28178 { 12116, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12116 = V_CMPSX_NEQ_F64_e32_gfx6_gfx7
28182 { 12120, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12120 = V_CMPSX_NGE_F64_e32_gfx6_gfx7
28186 { 12124, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12124 = V_CMPSX_NGT_F64_e32_gfx6_gfx7
28190 { 12128, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12128 = V_CMPSX_NLE_F64_e32_gfx6_gfx7
28194 { 12132, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12132 = V_CMPSX_NLG_F64_e32_gfx6_gfx7
28198 { 12136, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12136 = V_CMPSX_NLT_F64_e32_gfx6_gfx7
28202 { 12140, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12140 = V_CMPSX_O_F64_e32_gfx6_gfx7
28206 { 12144, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12144 = V_CMPSX_TRU_F64_e32_gfx6_gfx7
28210 { 12148, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12148 = V_CMPSX_U_F64_e32_gfx6_gfx7
28214 { 12152, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12152 = V_CMPS_EQ_F64_e32_gfx6_gfx7
28218 { 12156, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12156 = V_CMPS_F_F64_e32_gfx6_gfx7
28222 { 12160, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12160 = V_CMPS_GE_F64_e32_gfx6_gfx7
28226 { 12164, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12164 = V_CMPS_GT_F64_e32_gfx6_gfx7
28230 { 12168, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12168 = V_CMPS_LE_F64_e32_gfx6_gfx7
28234 { 12172, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12172 = V_CMPS_LG_F64_e32_gfx6_gfx7
28238 { 12176, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12176 = V_CMPS_LT_F64_e32_gfx6_gfx7
28242 { 12180, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12180 = V_CMPS_NEQ_F64_e32_gfx6_gfx7
28246 { 12184, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12184 = V_CMPS_NGE_F64_e32_gfx6_gfx7
28250 { 12188, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12188 = V_CMPS_NGT_F64_e32_gfx6_gfx7
28254 { 12192, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12192 = V_CMPS_NLE_F64_e32_gfx6_gfx7
28258 { 12196, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12196 = V_CMPS_NLG_F64_e32_gfx6_gfx7
28262 { 12200, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12200 = V_CMPS_NLT_F64_e32_gfx6_gfx7
28266 { 12204, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12204 = V_CMPS_O_F64_e32_gfx6_gfx7
28270 { 12208, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12208 = V_CMPS_TRU_F64_e32_gfx6_gfx7
28274 { 12212, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12212 = V_CMPS_U_F64_e32_gfx6_gfx7
28314 { 12252, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12252 = V_CMPX_EQ_F64_e32_gfx10
28315 { 12253, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12253 = V_CMPX_EQ_F64_e32_gfx6_gfx7
28316 { 12254, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12254 = V_CMPX_EQ_F64_e32_vi
28380 { 12318, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12318 = V_CMPX_F_F64_e32_gfx10
28381 { 12319, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12319 = V_CMPX_F_F64_e32_gfx6_gfx7
28382 { 12320, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12320 = V_CMPX_F_F64_e32_vi
28440 { 12378, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12378 = V_CMPX_GE_F64_e32_gfx10
28441 { 12379, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12379 = V_CMPX_GE_F64_e32_gfx6_gfx7
28442 { 12380, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12380 = V_CMPX_GE_F64_e32_vi
28506 { 12444, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12444 = V_CMPX_GT_F64_e32_gfx10
28507 { 12445, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12445 = V_CMPX_GT_F64_e32_gfx6_gfx7
28508 { 12446, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12446 = V_CMPX_GT_F64_e32_vi
28572 { 12510, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12510 = V_CMPX_LE_F64_e32_gfx10
28573 { 12511, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12511 = V_CMPX_LE_F64_e32_gfx6_gfx7
28574 { 12512, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12512 = V_CMPX_LE_F64_e32_vi
28638 { 12576, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12576 = V_CMPX_LG_F64_e32_gfx10
28639 { 12577, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12577 = V_CMPX_LG_F64_e32_gfx6_gfx7
28640 { 12578, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12578 = V_CMPX_LG_F64_e32_vi
28660 { 12598, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12598 = V_CMPX_LT_F64_e32_gfx10
28661 { 12599, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12599 = V_CMPX_LT_F64_e32_gfx6_gfx7
28662 { 12600, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12600 = V_CMPX_LT_F64_e32_vi
28726 { 12664, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12664 = V_CMPX_NEQ_F64_e32_gfx10
28727 { 12665, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12665 = V_CMPX_NEQ_F64_e32_gfx6_gfx7
28728 { 12666, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12666 = V_CMPX_NEQ_F64_e32_vi
28792 { 12730, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12730 = V_CMPX_NGE_F64_e32_gfx10
28793 { 12731, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12731 = V_CMPX_NGE_F64_e32_gfx6_gfx7
28794 { 12732, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12732 = V_CMPX_NGE_F64_e32_vi
28814 { 12752, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12752 = V_CMPX_NGT_F64_e32_gfx10
28815 { 12753, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12753 = V_CMPX_NGT_F64_e32_gfx6_gfx7
28816 { 12754, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12754 = V_CMPX_NGT_F64_e32_vi
28836 { 12774, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12774 = V_CMPX_NLE_F64_e32_gfx10
28837 { 12775, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12775 = V_CMPX_NLE_F64_e32_gfx6_gfx7
28838 { 12776, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12776 = V_CMPX_NLE_F64_e32_vi
28858 { 12796, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12796 = V_CMPX_NLG_F64_e32_gfx10
28859 { 12797, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12797 = V_CMPX_NLG_F64_e32_gfx6_gfx7
28860 { 12798, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12798 = V_CMPX_NLG_F64_e32_vi
28880 { 12818, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12818 = V_CMPX_NLT_F64_e32_gfx10
28881 { 12819, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12819 = V_CMPX_NLT_F64_e32_gfx6_gfx7
28882 { 12820, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12820 = V_CMPX_NLT_F64_e32_vi
28902 { 12840, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12840 = V_CMPX_O_F64_e32_gfx10
28903 { 12841, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12841 = V_CMPX_O_F64_e32_gfx6_gfx7
28904 { 12842, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12842 = V_CMPX_O_F64_e32_vi
28924 { 12862, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12862 = V_CMPX_TRU_F64_e32_gfx10
28925 { 12863, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12863 = V_CMPX_TRU_F64_e32_gfx6_gfx7
28926 { 12864, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12864 = V_CMPX_TRU_F64_e32_vi
28984 { 12922, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #12922 = V_CMPX_U_F64_e32_gfx10
28985 { 12923, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12923 = V_CMPX_U_F64_e32_gfx6_gfx7
28986 { 12924, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #12924 = V_CMPX_U_F64_e32_vi
29028 { 12966, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12966 = V_CMP_EQ_F64_e32_gfx10
29029 { 12967, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12967 = V_CMP_EQ_F64_e32_gfx6_gfx7
29030 { 12968, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #12968 = V_CMP_EQ_F64_e32_vi
29094 { 13032, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13032 = V_CMP_F_F64_e32_gfx10
29095 { 13033, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13033 = V_CMP_F_F64_e32_gfx6_gfx7
29096 { 13034, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13034 = V_CMP_F_F64_e32_vi
29154 { 13092, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13092 = V_CMP_GE_F64_e32_gfx10
29155 { 13093, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13093 = V_CMP_GE_F64_e32_gfx6_gfx7
29156 { 13094, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13094 = V_CMP_GE_F64_e32_vi
29220 { 13158, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13158 = V_CMP_GT_F64_e32_gfx10
29221 { 13159, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13159 = V_CMP_GT_F64_e32_gfx6_gfx7
29222 { 13160, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13160 = V_CMP_GT_F64_e32_vi
29286 { 13224, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13224 = V_CMP_LE_F64_e32_gfx10
29287 { 13225, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13225 = V_CMP_LE_F64_e32_gfx6_gfx7
29288 { 13226, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13226 = V_CMP_LE_F64_e32_vi
29352 { 13290, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13290 = V_CMP_LG_F64_e32_gfx10
29353 { 13291, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13291 = V_CMP_LG_F64_e32_gfx6_gfx7
29354 { 13292, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13292 = V_CMP_LG_F64_e32_vi
29374 { 13312, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13312 = V_CMP_LT_F64_e32_gfx10
29375 { 13313, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13313 = V_CMP_LT_F64_e32_gfx6_gfx7
29376 { 13314, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13314 = V_CMP_LT_F64_e32_vi
29440 { 13378, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13378 = V_CMP_NEQ_F64_e32_gfx10
29441 { 13379, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13379 = V_CMP_NEQ_F64_e32_gfx6_gfx7
29442 { 13380, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13380 = V_CMP_NEQ_F64_e32_vi
29506 { 13444, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13444 = V_CMP_NGE_F64_e32_gfx10
29507 { 13445, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13445 = V_CMP_NGE_F64_e32_gfx6_gfx7
29508 { 13446, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13446 = V_CMP_NGE_F64_e32_vi
29528 { 13466, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13466 = V_CMP_NGT_F64_e32_gfx10
29529 { 13467, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13467 = V_CMP_NGT_F64_e32_gfx6_gfx7
29530 { 13468, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13468 = V_CMP_NGT_F64_e32_vi
29550 { 13488, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13488 = V_CMP_NLE_F64_e32_gfx10
29551 { 13489, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13489 = V_CMP_NLE_F64_e32_gfx6_gfx7
29552 { 13490, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13490 = V_CMP_NLE_F64_e32_vi
29572 { 13510, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13510 = V_CMP_NLG_F64_e32_gfx10
29573 { 13511, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13511 = V_CMP_NLG_F64_e32_gfx6_gfx7
29574 { 13512, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13512 = V_CMP_NLG_F64_e32_vi
29594 { 13532, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13532 = V_CMP_NLT_F64_e32_gfx10
29595 { 13533, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13533 = V_CMP_NLT_F64_e32_gfx6_gfx7
29596 { 13534, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13534 = V_CMP_NLT_F64_e32_vi
29616 { 13554, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13554 = V_CMP_O_F64_e32_gfx10
29617 { 13555, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13555 = V_CMP_O_F64_e32_gfx6_gfx7
29618 { 13556, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13556 = V_CMP_O_F64_e32_vi
29638 { 13576, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13576 = V_CMP_TRU_F64_e32_gfx10
29639 { 13577, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13577 = V_CMP_TRU_F64_e32_gfx6_gfx7
29640 { 13578, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13578 = V_CMP_TRU_F64_e32_vi
29698 { 13636, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13636 = V_CMP_U_F64_e32_gfx10
29699 { 13637, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13637 = V_CMP_U_F64_e32_gfx6_gfx7
29700 { 13638, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #13638 = V_CMP_U_F64_e32_vi