|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18459 { 2397, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2397 = V_CMPSX_EQ_F32_sdwa
18469 { 2407, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2407 = V_CMPSX_F_F32_sdwa
18479 { 2417, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2417 = V_CMPSX_GE_F32_sdwa
18489 { 2427, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2427 = V_CMPSX_GT_F32_sdwa
18499 { 2437, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2437 = V_CMPSX_LE_F32_sdwa
18509 { 2447, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2447 = V_CMPSX_LG_F32_sdwa
18519 { 2457, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2457 = V_CMPSX_LT_F32_sdwa
18529 { 2467, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2467 = V_CMPSX_NEQ_F32_sdwa
18539 { 2477, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2477 = V_CMPSX_NGE_F32_sdwa
18549 { 2487, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2487 = V_CMPSX_NGT_F32_sdwa
18559 { 2497, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2497 = V_CMPSX_NLE_F32_sdwa
18569 { 2507, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2507 = V_CMPSX_NLG_F32_sdwa
18579 { 2517, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2517 = V_CMPSX_NLT_F32_sdwa
18589 { 2527, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2527 = V_CMPSX_O_F32_sdwa
18599 { 2537, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2537 = V_CMPSX_TRU_F32_sdwa
18609 { 2547, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2547 = V_CMPSX_U_F32_sdwa
18616 { 2554, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2554 = V_CMPS_EQ_F32_sdwa
18621 { 2559, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2559 = V_CMPS_F_F32_sdwa
18626 { 2564, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2564 = V_CMPS_GE_F32_sdwa
18631 { 2569, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2569 = V_CMPS_GT_F32_sdwa
18636 { 2574, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2574 = V_CMPS_LE_F32_sdwa
18641 { 2579, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2579 = V_CMPS_LG_F32_sdwa
18646 { 2584, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2584 = V_CMPS_LT_F32_sdwa
18651 { 2589, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2589 = V_CMPS_NEQ_F32_sdwa
18656 { 2594, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2594 = V_CMPS_NGE_F32_sdwa
18661 { 2599, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2599 = V_CMPS_NGT_F32_sdwa
18666 { 2604, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2604 = V_CMPS_NLE_F32_sdwa
18671 { 2609, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2609 = V_CMPS_NLG_F32_sdwa
18676 { 2614, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2614 = V_CMPS_NLT_F32_sdwa
18681 { 2619, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2619 = V_CMPS_O_F32_sdwa
18686 { 2624, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2624 = V_CMPS_TRU_F32_sdwa
18691 { 2629, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2629 = V_CMPS_U_F32_sdwa
18705 { 2643, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2643 = V_CMPX_CLASS_F32_sdwa
18721 { 2659, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2659 = V_CMPX_EQ_F32_sdwa
18769 { 2707, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2707 = V_CMPX_F_F32_sdwa
18817 { 2755, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2755 = V_CMPX_GE_F32_sdwa
18865 { 2803, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2803 = V_CMPX_GT_F32_sdwa
18913 { 2851, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2851 = V_CMPX_LE_F32_sdwa
18961 { 2899, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2899 = V_CMPX_LG_F32_sdwa
18977 { 2915, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2915 = V_CMPX_LT_F32_sdwa
19025 { 2963, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2963 = V_CMPX_NEQ_F32_sdwa
19073 { 3011, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3011 = V_CMPX_NGE_F32_sdwa
19089 { 3027, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3027 = V_CMPX_NGT_F32_sdwa
19105 { 3043, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3043 = V_CMPX_NLE_F32_sdwa
19121 { 3059, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3059 = V_CMPX_NLG_F32_sdwa
19137 { 3075, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3075 = V_CMPX_NLT_F32_sdwa
19153 { 3091, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3091 = V_CMPX_O_F32_sdwa
19169 { 3107, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3107 = V_CMPX_TRU_F32_sdwa
19217 { 3155, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3155 = V_CMPX_U_F32_sdwa
19227 { 3165, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3165 = V_CMP_CLASS_F32_sdwa
19235 { 3173, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3173 = V_CMP_EQ_F32_sdwa
19259 { 3197, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3197 = V_CMP_F_F32_sdwa
19283 { 3221, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3221 = V_CMP_GE_F32_sdwa
19307 { 3245, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3245 = V_CMP_GT_F32_sdwa
19331 { 3269, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3269 = V_CMP_LE_F32_sdwa
19355 { 3293, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3293 = V_CMP_LG_F32_sdwa
19363 { 3301, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3301 = V_CMP_LT_F32_sdwa
19387 { 3325, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3325 = V_CMP_NEQ_F32_sdwa
19411 { 3349, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3349 = V_CMP_NGE_F32_sdwa
19419 { 3357, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3357 = V_CMP_NGT_F32_sdwa
19427 { 3365, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3365 = V_CMP_NLE_F32_sdwa
19435 { 3373, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3373 = V_CMP_NLG_F32_sdwa
19443 { 3381, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3381 = V_CMP_NLT_F32_sdwa
19451 { 3389, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3389 = V_CMP_O_F32_sdwa
19459 { 3397, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3397 = V_CMP_TRU_F32_sdwa
19483 { 3421, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3421 = V_CMP_U_F32_sdwa
28290 { 12228, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12228 = V_CMPX_CLASS_F32_sdwa_gfx9
28291 { 12229, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12229 = V_CMPX_CLASS_F32_sdwa_vi
28312 { 12250, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12250 = V_CMPX_EQ_F32_sdwa_gfx9
28313 { 12251, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12251 = V_CMPX_EQ_F32_sdwa_vi
28378 { 12316, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12316 = V_CMPX_F_F32_sdwa_gfx9
28379 { 12317, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12317 = V_CMPX_F_F32_sdwa_vi
28438 { 12376, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12376 = V_CMPX_GE_F32_sdwa_gfx9
28439 { 12377, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12377 = V_CMPX_GE_F32_sdwa_vi
28504 { 12442, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12442 = V_CMPX_GT_F32_sdwa_gfx9
28505 { 12443, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12443 = V_CMPX_GT_F32_sdwa_vi
28570 { 12508, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12508 = V_CMPX_LE_F32_sdwa_gfx9
28571 { 12509, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12509 = V_CMPX_LE_F32_sdwa_vi
28636 { 12574, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12574 = V_CMPX_LG_F32_sdwa_gfx9
28637 { 12575, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12575 = V_CMPX_LG_F32_sdwa_vi
28658 { 12596, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12596 = V_CMPX_LT_F32_sdwa_gfx9
28659 { 12597, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12597 = V_CMPX_LT_F32_sdwa_vi
28724 { 12662, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12662 = V_CMPX_NEQ_F32_sdwa_gfx9
28725 { 12663, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12663 = V_CMPX_NEQ_F32_sdwa_vi
28790 { 12728, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12728 = V_CMPX_NGE_F32_sdwa_gfx9
28791 { 12729, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12729 = V_CMPX_NGE_F32_sdwa_vi
28812 { 12750, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12750 = V_CMPX_NGT_F32_sdwa_gfx9
28813 { 12751, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12751 = V_CMPX_NGT_F32_sdwa_vi
28834 { 12772, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12772 = V_CMPX_NLE_F32_sdwa_gfx9
28835 { 12773, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12773 = V_CMPX_NLE_F32_sdwa_vi
28856 { 12794, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12794 = V_CMPX_NLG_F32_sdwa_gfx9
28857 { 12795, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12795 = V_CMPX_NLG_F32_sdwa_vi
28878 { 12816, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12816 = V_CMPX_NLT_F32_sdwa_gfx9
28879 { 12817, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12817 = V_CMPX_NLT_F32_sdwa_vi
28900 { 12838, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12838 = V_CMPX_O_F32_sdwa_gfx9
28901 { 12839, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12839 = V_CMPX_O_F32_sdwa_vi
28922 { 12860, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12860 = V_CMPX_TRU_F32_sdwa_gfx9
28923 { 12861, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12861 = V_CMPX_TRU_F32_sdwa_vi
28982 { 12920, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12920 = V_CMPX_U_F32_sdwa_gfx9
28983 { 12921, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #12921 = V_CMPX_U_F32_sdwa_vi
29003 { 12941, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #12941 = V_CMP_CLASS_F32_sdwa_gfx10
29004 { 12942, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #12942 = V_CMP_CLASS_F32_sdwa_gfx9
29005 { 12943, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #12943 = V_CMP_CLASS_F32_sdwa_vi
29025 { 12963, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #12963 = V_CMP_EQ_F32_sdwa_gfx10
29026 { 12964, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #12964 = V_CMP_EQ_F32_sdwa_gfx9
29027 { 12965, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #12965 = V_CMP_EQ_F32_sdwa_vi
29091 { 13029, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13029 = V_CMP_F_F32_sdwa_gfx10
29092 { 13030, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13030 = V_CMP_F_F32_sdwa_gfx9
29093 { 13031, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13031 = V_CMP_F_F32_sdwa_vi
29151 { 13089, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13089 = V_CMP_GE_F32_sdwa_gfx10
29152 { 13090, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13090 = V_CMP_GE_F32_sdwa_gfx9
29153 { 13091, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13091 = V_CMP_GE_F32_sdwa_vi
29217 { 13155, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13155 = V_CMP_GT_F32_sdwa_gfx10
29218 { 13156, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13156 = V_CMP_GT_F32_sdwa_gfx9
29219 { 13157, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13157 = V_CMP_GT_F32_sdwa_vi
29283 { 13221, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13221 = V_CMP_LE_F32_sdwa_gfx10
29284 { 13222, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13222 = V_CMP_LE_F32_sdwa_gfx9
29285 { 13223, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13223 = V_CMP_LE_F32_sdwa_vi
29349 { 13287, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13287 = V_CMP_LG_F32_sdwa_gfx10
29350 { 13288, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13288 = V_CMP_LG_F32_sdwa_gfx9
29351 { 13289, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13289 = V_CMP_LG_F32_sdwa_vi
29371 { 13309, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13309 = V_CMP_LT_F32_sdwa_gfx10
29372 { 13310, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13310 = V_CMP_LT_F32_sdwa_gfx9
29373 { 13311, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13311 = V_CMP_LT_F32_sdwa_vi
29437 { 13375, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13375 = V_CMP_NEQ_F32_sdwa_gfx10
29438 { 13376, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13376 = V_CMP_NEQ_F32_sdwa_gfx9
29439 { 13377, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13377 = V_CMP_NEQ_F32_sdwa_vi
29503 { 13441, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13441 = V_CMP_NGE_F32_sdwa_gfx10
29504 { 13442, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13442 = V_CMP_NGE_F32_sdwa_gfx9
29505 { 13443, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13443 = V_CMP_NGE_F32_sdwa_vi
29525 { 13463, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13463 = V_CMP_NGT_F32_sdwa_gfx10
29526 { 13464, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13464 = V_CMP_NGT_F32_sdwa_gfx9
29527 { 13465, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13465 = V_CMP_NGT_F32_sdwa_vi
29547 { 13485, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13485 = V_CMP_NLE_F32_sdwa_gfx10
29548 { 13486, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13486 = V_CMP_NLE_F32_sdwa_gfx9
29549 { 13487, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13487 = V_CMP_NLE_F32_sdwa_vi
29569 { 13507, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13507 = V_CMP_NLG_F32_sdwa_gfx10
29570 { 13508, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13508 = V_CMP_NLG_F32_sdwa_gfx9
29571 { 13509, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13509 = V_CMP_NLG_F32_sdwa_vi
29591 { 13529, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13529 = V_CMP_NLT_F32_sdwa_gfx10
29592 { 13530, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13530 = V_CMP_NLT_F32_sdwa_gfx9
29593 { 13531, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13531 = V_CMP_NLT_F32_sdwa_vi
29613 { 13551, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13551 = V_CMP_O_F32_sdwa_gfx10
29614 { 13552, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13552 = V_CMP_O_F32_sdwa_gfx9
29615 { 13553, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13553 = V_CMP_O_F32_sdwa_vi
29635 { 13573, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13573 = V_CMP_TRU_F32_sdwa_gfx10
29636 { 13574, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13574 = V_CMP_TRU_F32_sdwa_gfx9
29637 { 13575, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13575 = V_CMP_TRU_F32_sdwa_vi
29695 { 13633, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13633 = V_CMP_U_F32_sdwa_gfx10
29696 { 13634, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13634 = V_CMP_U_F32_sdwa_gfx9
29697 { 13635, 8, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #13635 = V_CMP_U_F32_sdwa_vi