|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18451 { 2389, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #2389 = V_CEIL_F64_e64
19666 { 3604, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3604 = V_FLOOR_F64_e64
19695 { 3633, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3633 = V_FRACT_F64_e64
19715 { 3653, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3653 = V_FREXP_MANT_F64_e64
20027 { 3965, 5, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3965 = V_RCP_CLAMP_F64_e64
20037 { 3975, 5, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3975 = V_RCP_F64_e64
20056 { 3994, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3994 = V_RNDNE_F64_e64
20062 { 4000, 5, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #4000 = V_RSQ_CLAMP_F64_e64
20072 { 4010, 5, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #4010 = V_RSQ_F64_e64
20108 { 4046, 5, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #4046 = V_SQRT_F64_e64
20171 { 4109, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #4109 = V_TRUNC_F64_e64
28139 { 12077, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #12077 = V_CEIL_F64_e64_gfx10
28140 { 12078, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #12078 = V_CEIL_F64_e64_gfx7
28141 { 12079, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #12079 = V_CEIL_F64_e64_vi
30179 { 14117, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14117 = V_FLOOR_F64_e64_gfx10
30180 { 14118, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14118 = V_FLOOR_F64_e64_gfx7
30181 { 14119, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14119 = V_FLOOR_F64_e64_vi
30239 { 14177, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14177 = V_FRACT_F64_e64_gfx10
30240 { 14178, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14178 = V_FRACT_F64_e64_gfx6_gfx7
30241 { 14179, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14179 = V_FRACT_F64_e64_vi
30295 { 14233, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14233 = V_FREXP_MANT_F64_e64_gfx10
30296 { 14234, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14234 = V_FREXP_MANT_F64_e64_gfx6_gfx7
30297 { 14235, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14235 = V_FREXP_MANT_F64_e64_vi
30937 { 14875, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14875 = V_RCP_CLAMP_F64_e64_gfx6_gfx7
30963 { 14901, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14901 = V_RCP_F64_e64_gfx10
30964 { 14902, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14902 = V_RCP_F64_e64_gfx6_gfx7
30965 { 14903, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14903 = V_RCP_F64_e64_vi
31009 { 14947, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14947 = V_RNDNE_F64_e64_gfx10
31010 { 14948, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14948 = V_RNDNE_F64_e64_gfx7
31011 { 14949, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14949 = V_RNDNE_F64_e64_vi
31015 { 14953, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14953 = V_RSQ_CLAMP_F64_e64_gfx6_gfx7
31041 { 14979, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14979 = V_RSQ_F64_e64_gfx10
31042 { 14980, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14980 = V_RSQ_F64_e64_gfx6_gfx7
31043 { 14981, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #14981 = V_RSQ_F64_e64_vi
31119 { 15057, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #15057 = V_SQRT_F64_e64_gfx10
31120 { 15058, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #15058 = V_SQRT_F64_e64_gfx6_gfx7
31121 { 15059, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #15059 = V_SQRT_F64_e64_vi
31294 { 15232, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #15232 = V_TRUNC_F64_e64_gfx10
31295 { 15233, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #15233 = V_TRUNC_F64_e64_gfx7
31296 { 15234, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #15234 = V_TRUNC_F64_e64_vi