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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18450 { 2388, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2388 = V_CEIL_F64_e32
19665 { 3603, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3603 = V_FLOOR_F64_e32
19694 { 3632, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3632 = V_FRACT_F64_e32
19714 { 3652, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3652 = V_FREXP_MANT_F64_e32
20026 { 3964, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3964 = V_RCP_CLAMP_F64_e32
20036 { 3974, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3974 = V_RCP_F64_e32
20055 { 3993, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3993 = V_RNDNE_F64_e32
20061 { 3999, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3999 = V_RSQ_CLAMP_F64_e32
20071 { 4009, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #4009 = V_RSQ_F64_e32
20107 { 4045, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #4045 = V_SQRT_F64_e32
20170 { 4108, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #4108 = V_TRUNC_F64_e32
28136 { 12074, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #12074 = V_CEIL_F64_e32_gfx10
28137 { 12075, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #12075 = V_CEIL_F64_e32_gfx7
28138 { 12076, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #12076 = V_CEIL_F64_e32_vi
30176 { 14114, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14114 = V_FLOOR_F64_e32_gfx10
30177 { 14115, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14115 = V_FLOOR_F64_e32_gfx7
30178 { 14116, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14116 = V_FLOOR_F64_e32_vi
30236 { 14174, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14174 = V_FRACT_F64_e32_gfx10
30237 { 14175, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14175 = V_FRACT_F64_e32_gfx6_gfx7
30238 { 14176, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14176 = V_FRACT_F64_e32_vi
30292 { 14230, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14230 = V_FREXP_MANT_F64_e32_gfx10
30293 { 14231, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14231 = V_FREXP_MANT_F64_e32_gfx6_gfx7
30294 { 14232, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14232 = V_FREXP_MANT_F64_e32_vi
30936 { 14874, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14874 = V_RCP_CLAMP_F64_e32_gfx6_gfx7
30960 { 14898, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14898 = V_RCP_F64_e32_gfx10
30961 { 14899, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14899 = V_RCP_F64_e32_gfx6_gfx7
30962 { 14900, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14900 = V_RCP_F64_e32_vi
31006 { 14944, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14944 = V_RNDNE_F64_e32_gfx10
31007 { 14945, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14945 = V_RNDNE_F64_e32_gfx7
31008 { 14946, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14946 = V_RNDNE_F64_e32_vi
31014 { 14952, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14952 = V_RSQ_CLAMP_F64_e32_gfx6_gfx7
31038 { 14976, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14976 = V_RSQ_F64_e32_gfx10
31039 { 14977, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14977 = V_RSQ_F64_e32_gfx6_gfx7
31040 { 14978, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #14978 = V_RSQ_F64_e32_vi
31116 { 15054, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #15054 = V_SQRT_F64_e32_gfx10
31117 { 15055, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #15055 = V_SQRT_F64_e32_gfx6_gfx7
31118 { 15056, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #15056 = V_SQRT_F64_e32_vi
31291 { 15229, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #15229 = V_TRUNC_F64_e32_gfx10
31292 { 15230, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #15230 = V_TRUNC_F64_e32_gfx7
31293 { 15231, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #15231 = V_TRUNC_F64_e32_vi