|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18448 { 2386, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #2386 = V_CEIL_F32_e64
19497 { 3435, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3435 = V_COS_F32_e64
19505 { 3443, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3443 = V_CVT_F16_F32_e64
19553 { 3491, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3491 = V_CVT_FLR_I32_F32_e64
19561 { 3499, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3499 = V_CVT_I32_F32_e64
19594 { 3532, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3532 = V_CVT_RPI_I32_F32_e64
19602 { 3540, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3540 = V_CVT_U32_F32_e64
19639 { 3577, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3577 = V_EXP_F32_e64
19643 { 3581, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3581 = V_EXP_LEGACY_F32_e64
19663 { 3601, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3601 = V_FLOOR_F32_e64
19692 { 3630, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3630 = V_FRACT_F32_e64
19702 { 3640, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3640 = V_FREXP_EXP_I32_F32_e64
19712 { 3650, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3650 = V_FREXP_MANT_F32_e64
19737 { 3675, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3675 = V_LOG_CLAMP_F32_e64
19745 { 3683, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3683 = V_LOG_F32_e64
19749 { 3687, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3687 = V_LOG_LEGACY_F32_e64
20024 { 3962, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3962 = V_RCP_CLAMP_F32_e64
20034 { 3972, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3972 = V_RCP_F32_e64
20040 { 3978, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3978 = V_RCP_IFLAG_F32_e64
20044 { 3982, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3982 = V_RCP_LEGACY_F32_e64
20053 { 3991, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3991 = V_RNDNE_F32_e64
20059 { 3997, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3997 = V_RSQ_CLAMP_F32_e64
20069 { 4007, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #4007 = V_RSQ_F32_e64
20075 { 4013, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #4013 = V_RSQ_LEGACY_F32_e64
20097 { 4035, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #4035 = V_SIN_F32_e64
20105 { 4043, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #4043 = V_SQRT_F32_e64
20168 { 4106, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #4106 = V_TRUNC_F32_e64
28130 { 12068, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #12068 = V_CEIL_F32_e64_gfx10
28131 { 12069, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #12069 = V_CEIL_F32_e64_gfx6_gfx7
28132 { 12070, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #12070 = V_CEIL_F32_e64_vi
29738 { 13676, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13676 = V_COS_F32_e64_gfx10
29739 { 13677, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13677 = V_COS_F32_e64_gfx6_gfx7
29740 { 13678, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13678 = V_COS_F32_e64_vi
29762 { 13700, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13700 = V_CVT_F16_F32_e64_gfx10
29763 { 13701, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13701 = V_CVT_F16_F32_e64_gfx6_gfx7
29764 { 13702, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13702 = V_CVT_F16_F32_e64_vi
29902 { 13840, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13840 = V_CVT_FLR_I32_F32_e64_gfx10
29903 { 13841, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13841 = V_CVT_FLR_I32_F32_e64_gfx6_gfx7
29904 { 13842, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13842 = V_CVT_FLR_I32_F32_e64_vi
29924 { 13862, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13862 = V_CVT_I32_F32_e64_gfx10
29925 { 13863, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13863 = V_CVT_I32_F32_e64_gfx6_gfx7
29926 { 13864, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13864 = V_CVT_I32_F32_e64_vi
30005 { 13943, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13943 = V_CVT_RPI_I32_F32_e64_gfx10
30006 { 13944, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13944 = V_CVT_RPI_I32_F32_e64_gfx6_gfx7
30007 { 13945, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13945 = V_CVT_RPI_I32_F32_e64_vi
30027 { 13965, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13965 = V_CVT_U32_F32_e64_gfx10
30028 { 13966, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13966 = V_CVT_U32_F32_e64_gfx6_gfx7
30029 { 13967, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #13967 = V_CVT_U32_F32_e64_vi
30105 { 14043, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14043 = V_EXP_F32_e64_gfx10
30106 { 14044, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14044 = V_EXP_F32_e64_gfx6_gfx7
30107 { 14045, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14045 = V_EXP_F32_e64_vi
30114 { 14052, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14052 = V_EXP_LEGACY_F32_e64_gfx7
30115 { 14053, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14053 = V_EXP_LEGACY_F32_e64_vi
30170 { 14108, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14108 = V_FLOOR_F32_e64_gfx10
30171 { 14109, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14109 = V_FLOOR_F32_e64_gfx6_gfx7
30172 { 14110, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14110 = V_FLOOR_F32_e64_vi
30230 { 14168, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14168 = V_FRACT_F32_e64_gfx10
30231 { 14169, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14169 = V_FRACT_F32_e64_gfx6_gfx7
30232 { 14170, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14170 = V_FRACT_F32_e64_vi
30258 { 14196, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14196 = V_FREXP_EXP_I32_F32_e64_gfx10
30259 { 14197, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14197 = V_FREXP_EXP_I32_F32_e64_gfx6_gfx7
30260 { 14198, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14198 = V_FREXP_EXP_I32_F32_e64_vi
30286 { 14224, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14224 = V_FREXP_MANT_F32_e64_gfx10
30287 { 14225, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14225 = V_FREXP_MANT_F32_e64_gfx6_gfx7
30288 { 14226, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14226 = V_FREXP_MANT_F32_e64_vi
30345 { 14283, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14283 = V_LOG_CLAMP_F32_e64_gfx6_gfx7
30362 { 14300, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14300 = V_LOG_F32_e64_gfx10
30363 { 14301, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14301 = V_LOG_F32_e64_gfx6_gfx7
30364 { 14302, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14302 = V_LOG_F32_e64_vi
30371 { 14309, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14309 = V_LOG_LEGACY_F32_e64_gfx7
30372 { 14310, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14310 = V_LOG_LEGACY_F32_e64_vi
30935 { 14873, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14873 = V_RCP_CLAMP_F32_e64_gfx6_gfx7
30954 { 14892, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14892 = V_RCP_F32_e64_gfx10
30955 { 14893, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14893 = V_RCP_F32_e64_gfx6_gfx7
30956 { 14894, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14894 = V_RCP_F32_e64_vi
30972 { 14910, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14910 = V_RCP_IFLAG_F32_e64_gfx10
30973 { 14911, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14911 = V_RCP_IFLAG_F32_e64_gfx6_gfx7
30974 { 14912, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14912 = V_RCP_IFLAG_F32_e64_vi
30979 { 14917, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14917 = V_RCP_LEGACY_F32_e64_gfx6_gfx7
31000 { 14938, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14938 = V_RNDNE_F32_e64_gfx10
31001 { 14939, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14939 = V_RNDNE_F32_e64_gfx6_gfx7
31002 { 14940, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14940 = V_RNDNE_F32_e64_vi
31013 { 14951, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14951 = V_RSQ_CLAMP_F32_e64_gfx6_gfx7
31032 { 14970, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14970 = V_RSQ_F32_e64_gfx10
31033 { 14971, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14971 = V_RSQ_F32_e64_gfx6_gfx7
31034 { 14972, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14972 = V_RSQ_F32_e64_vi
31045 { 14983, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #14983 = V_RSQ_LEGACY_F32_e64_gfx6_gfx7
31088 { 15026, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #15026 = V_SIN_F32_e64_gfx10
31089 { 15027, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #15027 = V_SIN_F32_e64_gfx6_gfx7
31090 { 15028, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #15028 = V_SIN_F32_e64_vi
31110 { 15048, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #15048 = V_SQRT_F32_e64_gfx10
31111 { 15049, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #15049 = V_SQRT_F32_e64_gfx6_gfx7
31112 { 15050, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #15050 = V_SQRT_F32_e64_vi
31285 { 15223, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #15223 = V_TRUNC_F32_e64_gfx10
31286 { 15224, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #15224 = V_TRUNC_F32_e64_gfx6_gfx7
31287 { 15225, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #15225 = V_TRUNC_F32_e64_vi