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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18447 { 2385, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #2385 = V_CEIL_F32_e32
19496 { 3434, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3434 = V_COS_F32_e32
19504 { 3442, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3442 = V_CVT_F16_F32_e32
19552 { 3490, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3490 = V_CVT_FLR_I32_F32_e32
19560 { 3498, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3498 = V_CVT_I32_F32_e32
19593 { 3531, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3531 = V_CVT_RPI_I32_F32_e32
19601 { 3539, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3539 = V_CVT_U32_F32_e32
19638 { 3576, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3576 = V_EXP_F32_e32
19642 { 3580, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3580 = V_EXP_LEGACY_F32_e32
19662 { 3600, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3600 = V_FLOOR_F32_e32
19691 { 3629, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3629 = V_FRACT_F32_e32
19701 { 3639, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3639 = V_FREXP_EXP_I32_F32_e32
19711 { 3649, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3649 = V_FREXP_MANT_F32_e32
19736 { 3674, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3674 = V_LOG_CLAMP_F32_e32
19744 { 3682, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3682 = V_LOG_F32_e32
19748 { 3686, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3686 = V_LOG_LEGACY_F32_e32
20023 { 3961, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3961 = V_RCP_CLAMP_F32_e32
20033 { 3971, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3971 = V_RCP_F32_e32
20039 { 3977, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3977 = V_RCP_IFLAG_F32_e32
20043 { 3981, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3981 = V_RCP_LEGACY_F32_e32
20052 { 3990, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3990 = V_RNDNE_F32_e32
20058 { 3996, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3996 = V_RSQ_CLAMP_F32_e32
20068 { 4006, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #4006 = V_RSQ_F32_e32
20074 { 4012, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #4012 = V_RSQ_LEGACY_F32_e32
20096 { 4034, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #4034 = V_SIN_F32_e32
20104 { 4042, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #4042 = V_SQRT_F32_e32
20167 { 4105, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #4105 = V_TRUNC_F32_e32
28127 { 12065, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #12065 = V_CEIL_F32_e32_gfx10
28128 { 12066, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #12066 = V_CEIL_F32_e32_gfx6_gfx7
28129 { 12067, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #12067 = V_CEIL_F32_e32_vi
29735 { 13673, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13673 = V_COS_F32_e32_gfx10
29736 { 13674, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13674 = V_COS_F32_e32_gfx6_gfx7
29737 { 13675, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13675 = V_COS_F32_e32_vi
29759 { 13697, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13697 = V_CVT_F16_F32_e32_gfx10
29760 { 13698, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13698 = V_CVT_F16_F32_e32_gfx6_gfx7
29761 { 13699, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13699 = V_CVT_F16_F32_e32_vi
29899 { 13837, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13837 = V_CVT_FLR_I32_F32_e32_gfx10
29900 { 13838, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13838 = V_CVT_FLR_I32_F32_e32_gfx6_gfx7
29901 { 13839, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13839 = V_CVT_FLR_I32_F32_e32_vi
29921 { 13859, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13859 = V_CVT_I32_F32_e32_gfx10
29922 { 13860, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13860 = V_CVT_I32_F32_e32_gfx6_gfx7
29923 { 13861, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13861 = V_CVT_I32_F32_e32_vi
30002 { 13940, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13940 = V_CVT_RPI_I32_F32_e32_gfx10
30003 { 13941, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13941 = V_CVT_RPI_I32_F32_e32_gfx6_gfx7
30004 { 13942, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13942 = V_CVT_RPI_I32_F32_e32_vi
30024 { 13962, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13962 = V_CVT_U32_F32_e32_gfx10
30025 { 13963, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13963 = V_CVT_U32_F32_e32_gfx6_gfx7
30026 { 13964, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #13964 = V_CVT_U32_F32_e32_vi
30102 { 14040, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14040 = V_EXP_F32_e32_gfx10
30103 { 14041, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14041 = V_EXP_F32_e32_gfx6_gfx7
30104 { 14042, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14042 = V_EXP_F32_e32_vi
30112 { 14050, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14050 = V_EXP_LEGACY_F32_e32_gfx7
30113 { 14051, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14051 = V_EXP_LEGACY_F32_e32_vi
30167 { 14105, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14105 = V_FLOOR_F32_e32_gfx10
30168 { 14106, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14106 = V_FLOOR_F32_e32_gfx6_gfx7
30169 { 14107, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14107 = V_FLOOR_F32_e32_vi
30227 { 14165, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14165 = V_FRACT_F32_e32_gfx10
30228 { 14166, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14166 = V_FRACT_F32_e32_gfx6_gfx7
30229 { 14167, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14167 = V_FRACT_F32_e32_vi
30255 { 14193, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14193 = V_FREXP_EXP_I32_F32_e32_gfx10
30256 { 14194, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14194 = V_FREXP_EXP_I32_F32_e32_gfx6_gfx7
30257 { 14195, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14195 = V_FREXP_EXP_I32_F32_e32_vi
30283 { 14221, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14221 = V_FREXP_MANT_F32_e32_gfx10
30284 { 14222, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14222 = V_FREXP_MANT_F32_e32_gfx6_gfx7
30285 { 14223, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14223 = V_FREXP_MANT_F32_e32_vi
30344 { 14282, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14282 = V_LOG_CLAMP_F32_e32_gfx6_gfx7
30359 { 14297, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14297 = V_LOG_F32_e32_gfx10
30360 { 14298, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14298 = V_LOG_F32_e32_gfx6_gfx7
30361 { 14299, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14299 = V_LOG_F32_e32_vi
30369 { 14307, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14307 = V_LOG_LEGACY_F32_e32_gfx7
30370 { 14308, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14308 = V_LOG_LEGACY_F32_e32_vi
30934 { 14872, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14872 = V_RCP_CLAMP_F32_e32_gfx6_gfx7
30951 { 14889, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14889 = V_RCP_F32_e32_gfx10
30952 { 14890, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14890 = V_RCP_F32_e32_gfx6_gfx7
30953 { 14891, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14891 = V_RCP_F32_e32_vi
30969 { 14907, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14907 = V_RCP_IFLAG_F32_e32_gfx10
30970 { 14908, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14908 = V_RCP_IFLAG_F32_e32_gfx6_gfx7
30971 { 14909, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14909 = V_RCP_IFLAG_F32_e32_vi
30978 { 14916, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14916 = V_RCP_LEGACY_F32_e32_gfx6_gfx7
30997 { 14935, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14935 = V_RNDNE_F32_e32_gfx10
30998 { 14936, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14936 = V_RNDNE_F32_e32_gfx6_gfx7
30999 { 14937, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14937 = V_RNDNE_F32_e32_vi
31012 { 14950, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14950 = V_RSQ_CLAMP_F32_e32_gfx6_gfx7
31029 { 14967, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14967 = V_RSQ_F32_e32_gfx10
31030 { 14968, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14968 = V_RSQ_F32_e32_gfx6_gfx7
31031 { 14969, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14969 = V_RSQ_F32_e32_vi
31044 { 14982, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #14982 = V_RSQ_LEGACY_F32_e32_gfx6_gfx7
31085 { 15023, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #15023 = V_SIN_F32_e32_gfx10
31086 { 15024, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #15024 = V_SIN_F32_e32_gfx6_gfx7
31087 { 15025, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #15025 = V_SIN_F32_e32_vi
31107 { 15045, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #15045 = V_SQRT_F32_e32_gfx10
31108 { 15046, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #15046 = V_SQRT_F32_e32_gfx6_gfx7
31109 { 15047, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #15047 = V_SQRT_F32_e32_vi
31282 { 15220, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #15220 = V_TRUNC_F32_e32_gfx10
31283 { 15221, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #15221 = V_TRUNC_F32_e32_gfx6_gfx7
31284 { 15222, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #15222 = V_TRUNC_F32_e32_vi