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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18444 { 2382, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2382 = V_CEIL_F16_e64
19493 { 3431, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3431 = V_COS_F16_e64
19517 { 3455, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3455 = V_CVT_F32_F16_e64
19557 { 3495, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3495 = V_CVT_I16_F16_e64
19567 { 3505, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3505 = V_CVT_NORM_I16_F16_e64
19571 { 3509, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3509 = V_CVT_NORM_U16_F16_e64
19598 { 3536, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3536 = V_CVT_U16_F16_e64
19635 { 3573, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3573 = V_EXP_F16_e64
19659 { 3597, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3597 = V_FLOOR_F16_e64
19688 { 3626, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3626 = V_FRACT_F16_e64
19698 { 3636, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3636 = V_FREXP_EXP_I16_F16_e64
19708 { 3646, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3646 = V_FREXP_MANT_F16_e64
19741 { 3679, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3679 = V_LOG_F16_e64
20030 { 3968, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3968 = V_RCP_F16_e64
20049 { 3987, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3987 = V_RNDNE_F16_e64
20065 { 4003, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #4003 = V_RSQ_F16_e64
20093 { 4031, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #4031 = V_SIN_F16_e64
20101 { 4039, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #4039 = V_SQRT_F16_e64
20164 { 4102, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #4102 = V_TRUNC_F16_e64
28119 { 12057, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #12057 = V_CEIL_F16_e64_gfx10
28120 { 12058, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #12058 = V_CEIL_F16_e64_vi
29727 { 13665, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13665 = V_COS_F16_e64_gfx10
29728 { 13666, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13666 = V_COS_F16_e64_vi
29794 { 13732, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13732 = V_CVT_F32_F16_e64_gfx10
29795 { 13733, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13733 = V_CVT_F32_F16_e64_gfx6_gfx7
29796 { 13734, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13734 = V_CVT_F32_F16_e64_vi
29913 { 13851, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13851 = V_CVT_I16_F16_e64_gfx10
29914 { 13852, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13852 = V_CVT_I16_F16_e64_vi
29941 { 13879, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13879 = V_CVT_NORM_I16_F16_e64_gfx10
29942 { 13880, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13880 = V_CVT_NORM_I16_F16_e64_vi
29951 { 13889, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13889 = V_CVT_NORM_U16_F16_e64_gfx10
29952 { 13890, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13890 = V_CVT_NORM_U16_F16_e64_vi
30016 { 13954, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13954 = V_CVT_U16_F16_e64_gfx10
30017 { 13955, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #13955 = V_CVT_U16_F16_e64_vi
30094 { 14032, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14032 = V_EXP_F16_e64_gfx10
30095 { 14033, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14033 = V_EXP_F16_e64_vi
30159 { 14097, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14097 = V_FLOOR_F16_e64_gfx10
30160 { 14098, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14098 = V_FLOOR_F16_e64_vi
30219 { 14157, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14157 = V_FRACT_F16_e64_gfx10
30220 { 14158, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14158 = V_FRACT_F16_e64_vi
30247 { 14185, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14185 = V_FREXP_EXP_I16_F16_e64_gfx10
30248 { 14186, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14186 = V_FREXP_EXP_I16_F16_e64_vi
30275 { 14213, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14213 = V_FREXP_MANT_F16_e64_gfx10
30276 { 14214, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14214 = V_FREXP_MANT_F16_e64_vi
30351 { 14289, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14289 = V_LOG_F16_e64_gfx10
30352 { 14290, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14290 = V_LOG_F16_e64_vi
30943 { 14881, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14881 = V_RCP_F16_e64_gfx10
30944 { 14882, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14882 = V_RCP_F16_e64_vi
30989 { 14927, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14927 = V_RNDNE_F16_e64_gfx10
30990 { 14928, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14928 = V_RNDNE_F16_e64_vi
31021 { 14959, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14959 = V_RSQ_F16_e64_gfx10
31022 { 14960, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #14960 = V_RSQ_F16_e64_vi
31077 { 15015, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #15015 = V_SIN_F16_e64_gfx10
31078 { 15016, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #15016 = V_SIN_F16_e64_vi
31099 { 15037, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #15037 = V_SQRT_F16_e64_gfx10
31100 { 15038, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #15038 = V_SQRT_F16_e64_vi
31274 { 15212, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #15212 = V_TRUNC_F16_e64_gfx10
31275 { 15213, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #15213 = V_TRUNC_F16_e64_vi