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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18443 { 2381, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #2381 = V_CEIL_F16_e32
19492 { 3430, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3430 = V_COS_F16_e32
19516 { 3454, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3454 = V_CVT_F32_F16_e32
19556 { 3494, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3494 = V_CVT_I16_F16_e32
19566 { 3504, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3504 = V_CVT_NORM_I16_F16_e32
19570 { 3508, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3508 = V_CVT_NORM_U16_F16_e32
19597 { 3535, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3535 = V_CVT_U16_F16_e32
19634 { 3572, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3572 = V_EXP_F16_e32
19658 { 3596, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3596 = V_FLOOR_F16_e32
19687 { 3625, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3625 = V_FRACT_F16_e32
19697 { 3635, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3635 = V_FREXP_EXP_I16_F16_e32
19707 { 3645, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3645 = V_FREXP_MANT_F16_e32
19740 { 3678, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3678 = V_LOG_F16_e32
20029 { 3967, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3967 = V_RCP_F16_e32
20048 { 3986, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3986 = V_RNDNE_F16_e32
20064 { 4002, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #4002 = V_RSQ_F16_e32
20092 { 4030, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #4030 = V_SIN_F16_e32
20100 { 4038, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #4038 = V_SQRT_F16_e32
20163 { 4101, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #4101 = V_TRUNC_F16_e32
28117 { 12055, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #12055 = V_CEIL_F16_e32_gfx10
28118 { 12056, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #12056 = V_CEIL_F16_e32_vi
29725 { 13663, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13663 = V_COS_F16_e32_gfx10
29726 { 13664, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13664 = V_COS_F16_e32_vi
29791 { 13729, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13729 = V_CVT_F32_F16_e32_gfx10
29792 { 13730, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13730 = V_CVT_F32_F16_e32_gfx6_gfx7
29793 { 13731, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13731 = V_CVT_F32_F16_e32_vi
29911 { 13849, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13849 = V_CVT_I16_F16_e32_gfx10
29912 { 13850, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13850 = V_CVT_I16_F16_e32_vi
29939 { 13877, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13877 = V_CVT_NORM_I16_F16_e32_gfx10
29940 { 13878, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13878 = V_CVT_NORM_I16_F16_e32_vi
29949 { 13887, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13887 = V_CVT_NORM_U16_F16_e32_gfx10
29950 { 13888, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13888 = V_CVT_NORM_U16_F16_e32_vi
30014 { 13952, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13952 = V_CVT_U16_F16_e32_gfx10
30015 { 13953, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #13953 = V_CVT_U16_F16_e32_vi
30092 { 14030, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14030 = V_EXP_F16_e32_gfx10
30093 { 14031, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14031 = V_EXP_F16_e32_vi
30157 { 14095, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14095 = V_FLOOR_F16_e32_gfx10
30158 { 14096, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14096 = V_FLOOR_F16_e32_vi
30217 { 14155, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14155 = V_FRACT_F16_e32_gfx10
30218 { 14156, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14156 = V_FRACT_F16_e32_vi
30245 { 14183, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14183 = V_FREXP_EXP_I16_F16_e32_gfx10
30246 { 14184, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14184 = V_FREXP_EXP_I16_F16_e32_vi
30273 { 14211, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14211 = V_FREXP_MANT_F16_e32_gfx10
30274 { 14212, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14212 = V_FREXP_MANT_F16_e32_vi
30349 { 14287, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14287 = V_LOG_F16_e32_gfx10
30350 { 14288, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14288 = V_LOG_F16_e32_vi
30941 { 14879, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14879 = V_RCP_F16_e32_gfx10
30942 { 14880, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14880 = V_RCP_F16_e32_vi
30987 { 14925, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14925 = V_RNDNE_F16_e32_gfx10
30988 { 14926, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14926 = V_RNDNE_F16_e32_vi
31019 { 14957, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14957 = V_RSQ_F16_e32_gfx10
31020 { 14958, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #14958 = V_RSQ_F16_e32_vi
31075 { 15013, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #15013 = V_SIN_F16_e32_gfx10
31076 { 15014, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #15014 = V_SIN_F16_e32_vi
31097 { 15035, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #15035 = V_SQRT_F16_e32_gfx10
31098 { 15036, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #15036 = V_SQRT_F16_e32_vi
31272 { 15210, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #15210 = V_TRUNC_F16_e32_gfx10
31273 { 15211, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #15211 = V_TRUNC_F16_e32_vi