|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18442 { 2380, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2380 = V_CEIL_F16_dpp
18446 { 2384, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2384 = V_CEIL_F32_dpp
19491 { 3429, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3429 = V_COS_F16_dpp
19495 { 3433, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3433 = V_COS_F32_dpp
19503 { 3441, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3441 = V_CVT_F16_F32_dpp
19515 { 3453, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3453 = V_CVT_F32_F16_dpp
19551 { 3489, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3489 = V_CVT_FLR_I32_F32_dpp
19555 { 3493, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3493 = V_CVT_I16_F16_dpp
19559 { 3497, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3497 = V_CVT_I32_F32_dpp
19565 { 3503, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3503 = V_CVT_NORM_I16_F16_dpp
19569 { 3507, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3507 = V_CVT_NORM_U16_F16_dpp
19592 { 3530, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3530 = V_CVT_RPI_I32_F32_dpp
19596 { 3534, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3534 = V_CVT_U16_F16_dpp
19600 { 3538, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3538 = V_CVT_U32_F32_dpp
19633 { 3571, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3571 = V_EXP_F16_dpp
19637 { 3575, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3575 = V_EXP_F32_dpp
19641 { 3579, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3579 = V_EXP_LEGACY_F32_dpp
19657 { 3595, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3595 = V_FLOOR_F16_dpp
19661 { 3599, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3599 = V_FLOOR_F32_dpp
19686 { 3624, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3624 = V_FRACT_F16_dpp
19690 { 3628, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3628 = V_FRACT_F32_dpp
19696 { 3634, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3634 = V_FREXP_EXP_I16_F16_dpp
19700 { 3638, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3638 = V_FREXP_EXP_I32_F32_dpp
19706 { 3644, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3644 = V_FREXP_MANT_F16_dpp
19710 { 3648, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3648 = V_FREXP_MANT_F32_dpp
19735 { 3673, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3673 = V_LOG_CLAMP_F32_dpp
19739 { 3677, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3677 = V_LOG_F16_dpp
19743 { 3681, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3681 = V_LOG_F32_dpp
19747 { 3685, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3685 = V_LOG_LEGACY_F32_dpp
20022 { 3960, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3960 = V_RCP_CLAMP_F32_dpp
20028 { 3966, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3966 = V_RCP_F16_dpp
20032 { 3970, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3970 = V_RCP_F32_dpp
20038 { 3976, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3976 = V_RCP_IFLAG_F32_dpp
20042 { 3980, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3980 = V_RCP_LEGACY_F32_dpp
20047 { 3985, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3985 = V_RNDNE_F16_dpp
20051 { 3989, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3989 = V_RNDNE_F32_dpp
20057 { 3995, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3995 = V_RSQ_CLAMP_F32_dpp
20063 { 4001, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4001 = V_RSQ_F16_dpp
20067 { 4005, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4005 = V_RSQ_F32_dpp
20073 { 4011, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4011 = V_RSQ_LEGACY_F32_dpp
20091 { 4029, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4029 = V_SIN_F16_dpp
20095 { 4033, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4033 = V_SIN_F32_dpp
20099 { 4037, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4037 = V_SQRT_F16_dpp
20103 { 4041, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4041 = V_SQRT_F32_dpp
20162 { 4100, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4100 = V_TRUNC_F16_dpp
20166 { 4104, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4104 = V_TRUNC_F32_dpp
28116 { 12054, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #12054 = V_CEIL_F16_dpp_vi
28126 { 12064, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #12064 = V_CEIL_F32_dpp_vi
29724 { 13662, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13662 = V_COS_F16_dpp_vi
29734 { 13672, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13672 = V_COS_F32_dpp_vi
29758 { 13696, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13696 = V_CVT_F16_F32_dpp_vi
29790 { 13728, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13728 = V_CVT_F32_F16_dpp_vi
29898 { 13836, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13836 = V_CVT_FLR_I32_F32_dpp_vi
29910 { 13848, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13848 = V_CVT_I16_F16_dpp_vi
29920 { 13858, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13858 = V_CVT_I32_F32_dpp_vi
29938 { 13876, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13876 = V_CVT_NORM_I16_F16_dpp_vi
29948 { 13886, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13886 = V_CVT_NORM_U16_F16_dpp_vi
30001 { 13939, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13939 = V_CVT_RPI_I32_F32_dpp_vi
30013 { 13951, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13951 = V_CVT_U16_F16_dpp_vi
30023 { 13961, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #13961 = V_CVT_U32_F32_dpp_vi
30091 { 14029, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14029 = V_EXP_F16_dpp_vi
30101 { 14039, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14039 = V_EXP_F32_dpp_vi
30111 { 14049, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14049 = V_EXP_LEGACY_F32_dpp_vi
30156 { 14094, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14094 = V_FLOOR_F16_dpp_vi
30166 { 14104, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14104 = V_FLOOR_F32_dpp_vi
30216 { 14154, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14154 = V_FRACT_F16_dpp_vi
30226 { 14164, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14164 = V_FRACT_F32_dpp_vi
30244 { 14182, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14182 = V_FREXP_EXP_I16_F16_dpp_vi
30254 { 14192, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14192 = V_FREXP_EXP_I32_F32_dpp_vi
30272 { 14210, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14210 = V_FREXP_MANT_F16_dpp_vi
30282 { 14220, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14220 = V_FREXP_MANT_F32_dpp_vi
30348 { 14286, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14286 = V_LOG_F16_dpp_vi
30358 { 14296, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14296 = V_LOG_F32_dpp_vi
30368 { 14306, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14306 = V_LOG_LEGACY_F32_dpp_vi
30940 { 14878, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14878 = V_RCP_F16_dpp_vi
30950 { 14888, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14888 = V_RCP_F32_dpp_vi
30968 { 14906, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14906 = V_RCP_IFLAG_F32_dpp_vi
30986 { 14924, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14924 = V_RNDNE_F16_dpp_vi
30996 { 14934, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14934 = V_RNDNE_F32_dpp_vi
31018 { 14956, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14956 = V_RSQ_F16_dpp_vi
31028 { 14966, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #14966 = V_RSQ_F32_dpp_vi
31074 { 15012, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #15012 = V_SIN_F16_dpp_vi
31084 { 15022, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #15022 = V_SIN_F32_dpp_vi
31096 { 15034, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #15034 = V_SQRT_F16_dpp_vi
31106 { 15044, 8, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #15044 = V_SQRT_F32_dpp_vi
31271 { 15209, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #15209 = V_TRUNC_F16_dpp_vi
31281 { 15219, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #15219 = V_TRUNC_F32_dpp_vi