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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18441 { 2379, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #2379 = V_BFREV_B32_sdwa
19648 { 3586, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3586 = V_FFBH_I32_sdwa
19652 { 3590, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3590 = V_FFBH_U32_sdwa
19656 { 3594, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3594 = V_FFBL_B32_sdwa
19931 { 3869, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3869 = V_MOV_B32_sdwa
19937 { 3875, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3875 = V_MOV_FED_B32_sdwa
19985 { 3923, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3923 = V_NOT_B32_sdwa
20084 { 4022, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #4022 = V_SAT_PK_U8_I16_sdwa
20088 { 4026, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #4026 = V_SCREEN_PARTITION_4SE_B32_sdwa
28111 { 12049, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #12049 = V_BFREV_B32_sdwa_gfx10
28112 { 12050, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #12050 = V_BFREV_B32_sdwa_gfx9
28113 { 12051, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #12051 = V_BFREV_B32_sdwa_vi
30127 { 14065, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14065 = V_FFBH_I32_sdwa_gfx10
30128 { 14066, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14066 = V_FFBH_I32_sdwa_gfx9
30129 { 14067, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14067 = V_FFBH_I32_sdwa_vi
30139 { 14077, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14077 = V_FFBH_U32_sdwa_gfx10
30140 { 14078, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14078 = V_FFBH_U32_sdwa_gfx9
30141 { 14079, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14079 = V_FFBH_U32_sdwa_vi
30151 { 14089, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14089 = V_FFBL_B32_sdwa_gfx10
30152 { 14090, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14090 = V_FFBL_B32_sdwa_gfx9
30153 { 14091, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14091 = V_FFBL_B32_sdwa_vi
30718 { 14656, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14656 = V_MOV_B32_sdwa_gfx10
30719 { 14657, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14657 = V_MOV_B32_sdwa_gfx9
30720 { 14658, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14658 = V_MOV_B32_sdwa_vi
30730 { 14668, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14668 = V_MOV_FED_B32_sdwa_gfx10
30731 { 14669, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14669 = V_MOV_FED_B32_sdwa_gfx9
30732 { 14670, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14670 = V_MOV_FED_B32_sdwa_vi
30865 { 14803, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14803 = V_NOT_B32_sdwa_gfx10
30866 { 14804, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14804 = V_NOT_B32_sdwa_gfx9
30867 { 14805, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #14805 = V_NOT_B32_sdwa_vi
31065 { 15003, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #15003 = V_SAT_PK_U8_I16_sdwa_gfx10
31066 { 15004, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #15004 = V_SAT_PK_U8_I16_sdwa_gfx9
31067 { 15005, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #15005 = V_SAT_PK_U8_I16_sdwa_vi
31071 { 15009, 7, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #15009 = V_SCREEN_PARTITION_4SE_B32_sdwa_gfx9