|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18439 { 2377, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #2377 = V_BFREV_B32_e32
18440 { 2378, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #2378 = V_BFREV_B32_e64
19522 { 3460, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3460 = V_CVT_F32_I32_e32
19526 { 3464, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3464 = V_CVT_F32_U32_e32
19530 { 3468, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3468 = V_CVT_F32_UBYTE0_e32
19534 { 3472, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3472 = V_CVT_F32_UBYTE1_e32
19538 { 3476, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3476 = V_CVT_F32_UBYTE2_e32
19542 { 3480, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3480 = V_CVT_F32_UBYTE3_e32
19574 { 3512, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3512 = V_CVT_OFF_F32_I4_e32
19646 { 3584, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3584 = V_FFBH_I32_e32
19647 { 3585, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3585 = V_FFBH_I32_e64
19650 { 3588, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3588 = V_FFBH_U32_e32
19651 { 3589, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3589 = V_FFBH_U32_e64
19654 { 3592, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3592 = V_FFBL_B32_e32
19655 { 3593, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3593 = V_FFBL_B32_e64
19919 { 3857, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3857 = V_MOVRELD_B32_e32
19920 { 3858, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3858 = V_MOVRELD_B32_e64
19921 { 3859, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList10, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3859 = V_MOVRELSD_2_B32_e32
19922 { 3860, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList10, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3860 = V_MOVRELSD_2_B32_e64
19923 { 3861, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3861 = V_MOVRELSD_B32_e32
19924 { 3862, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3862 = V_MOVRELSD_B32_e64
19928 { 3866, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3866 = V_MOV_B32_e32
19929 { 3867, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3867 = V_MOV_B32_e64
19930 { 3868, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3868 = V_MOV_B32_indirect
19935 { 3873, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3873 = V_MOV_FED_B32_e32
19936 { 3874, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3874 = V_MOV_FED_B32_e64
19983 { 3921, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3921 = V_NOT_B32_e32
19984 { 3922, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3922 = V_NOT_B32_e64
20082 { 4020, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #4020 = V_SAT_PK_U8_I16_e32
20083 { 4021, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #4021 = V_SAT_PK_U8_I16_e64
20086 { 4024, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #4024 = V_SCREEN_PARTITION_4SE_B32_e32
20087 { 4025, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #4025 = V_SCREEN_PARTITION_4SE_B32_e64
28105 { 12043, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #12043 = V_BFREV_B32_e32_gfx10
28106 { 12044, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #12044 = V_BFREV_B32_e32_gfx6_gfx7
28107 { 12045, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #12045 = V_BFREV_B32_e32_vi
28108 { 12046, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #12046 = V_BFREV_B32_e64_gfx10
28109 { 12047, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #12047 = V_BFREV_B32_e64_gfx6_gfx7
28110 { 12048, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #12048 = V_BFREV_B32_e64_vi
29809 { 13747, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13747 = V_CVT_F32_I32_e32_gfx10
29810 { 13748, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13748 = V_CVT_F32_I32_e32_gfx6_gfx7
29811 { 13749, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13749 = V_CVT_F32_I32_e32_vi
29821 { 13759, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13759 = V_CVT_F32_U32_e32_gfx10
29822 { 13760, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13760 = V_CVT_F32_U32_e32_gfx6_gfx7
29823 { 13761, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13761 = V_CVT_F32_U32_e32_vi
29833 { 13771, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13771 = V_CVT_F32_UBYTE0_e32_gfx10
29834 { 13772, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13772 = V_CVT_F32_UBYTE0_e32_gfx6_gfx7
29835 { 13773, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13773 = V_CVT_F32_UBYTE0_e32_vi
29845 { 13783, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13783 = V_CVT_F32_UBYTE1_e32_gfx10
29846 { 13784, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13784 = V_CVT_F32_UBYTE1_e32_gfx6_gfx7
29847 { 13785, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13785 = V_CVT_F32_UBYTE1_e32_vi
29857 { 13795, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13795 = V_CVT_F32_UBYTE2_e32_gfx10
29858 { 13796, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13796 = V_CVT_F32_UBYTE2_e32_gfx6_gfx7
29859 { 13797, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13797 = V_CVT_F32_UBYTE2_e32_vi
29869 { 13807, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13807 = V_CVT_F32_UBYTE3_e32_gfx10
29870 { 13808, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13808 = V_CVT_F32_UBYTE3_e32_gfx6_gfx7
29871 { 13809, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13809 = V_CVT_F32_UBYTE3_e32_vi
29959 { 13897, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13897 = V_CVT_OFF_F32_I4_e32_gfx10
29960 { 13898, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13898 = V_CVT_OFF_F32_I4_e32_gfx6_gfx7
29961 { 13899, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #13899 = V_CVT_OFF_F32_I4_e32_vi
30121 { 14059, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14059 = V_FFBH_I32_e32_gfx10
30122 { 14060, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14060 = V_FFBH_I32_e32_gfx6_gfx7
30123 { 14061, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14061 = V_FFBH_I32_e32_vi
30124 { 14062, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14062 = V_FFBH_I32_e64_gfx10
30125 { 14063, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14063 = V_FFBH_I32_e64_gfx6_gfx7
30126 { 14064, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14064 = V_FFBH_I32_e64_vi
30133 { 14071, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14071 = V_FFBH_U32_e32_gfx10
30134 { 14072, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14072 = V_FFBH_U32_e32_gfx6_gfx7
30135 { 14073, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14073 = V_FFBH_U32_e32_vi
30136 { 14074, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14074 = V_FFBH_U32_e64_gfx10
30137 { 14075, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14075 = V_FFBH_U32_e64_gfx6_gfx7
30138 { 14076, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14076 = V_FFBH_U32_e64_vi
30145 { 14083, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14083 = V_FFBL_B32_e32_gfx10
30146 { 14084, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14084 = V_FFBL_B32_e32_gfx6_gfx7
30147 { 14085, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14085 = V_FFBL_B32_e32_vi
30148 { 14086, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14086 = V_FFBL_B32_e64_gfx10
30149 { 14087, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14087 = V_FFBL_B32_e64_gfx6_gfx7
30150 { 14088, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14088 = V_FFBL_B32_e64_vi
30689 { 14627, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14627 = V_MOVRELD_B32_e32_gfx10
30690 { 14628, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14628 = V_MOVRELD_B32_e32_gfx6_gfx7
30691 { 14629, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14629 = V_MOVRELD_B32_e32_vi
30692 { 14630, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14630 = V_MOVRELD_B32_e64_gfx10
30693 { 14631, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14631 = V_MOVRELD_B32_e64_gfx6_gfx7
30694 { 14632, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14632 = V_MOVRELD_B32_e64_vi
30695 { 14633, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList10, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14633 = V_MOVRELSD_2_B32_e32_gfx10
30696 { 14634, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList10, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14634 = V_MOVRELSD_2_B32_e64_gfx10
30697 { 14635, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14635 = V_MOVRELSD_B32_e32_gfx10
30698 { 14636, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14636 = V_MOVRELSD_B32_e32_gfx6_gfx7
30699 { 14637, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14637 = V_MOVRELSD_B32_e32_vi
30700 { 14638, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14638 = V_MOVRELSD_B32_e64_gfx10
30701 { 14639, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14639 = V_MOVRELSD_B32_e64_gfx6_gfx7
30702 { 14640, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14640 = V_MOVRELSD_B32_e64_vi
30712 { 14650, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14650 = V_MOV_B32_e32_gfx10
30713 { 14651, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14651 = V_MOV_B32_e32_gfx6_gfx7
30714 { 14652, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14652 = V_MOV_B32_e32_vi
30715 { 14653, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14653 = V_MOV_B32_e64_gfx10
30716 { 14654, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14654 = V_MOV_B32_e64_gfx6_gfx7
30717 { 14655, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14655 = V_MOV_B32_e64_vi
30724 { 14662, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14662 = V_MOV_FED_B32_e32_gfx10
30725 { 14663, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14663 = V_MOV_FED_B32_e32_gfx6_gfx7
30726 { 14664, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14664 = V_MOV_FED_B32_e32_vi
30727 { 14665, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14665 = V_MOV_FED_B32_e64_gfx10
30728 { 14666, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14666 = V_MOV_FED_B32_e64_gfx6_gfx7
30729 { 14667, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14667 = V_MOV_FED_B32_e64_vi
30859 { 14797, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14797 = V_NOT_B32_e32_gfx10
30860 { 14798, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14798 = V_NOT_B32_e32_gfx6_gfx7
30861 { 14799, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14799 = V_NOT_B32_e32_vi
30862 { 14800, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14800 = V_NOT_B32_e64_gfx10
30863 { 14801, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14801 = V_NOT_B32_e64_gfx6_gfx7
30864 { 14802, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14802 = V_NOT_B32_e64_vi
31061 { 14999, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14999 = V_SAT_PK_U8_I16_e32_gfx10
31062 { 15000, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #15000 = V_SAT_PK_U8_I16_e32_vi
31063 { 15001, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #15001 = V_SAT_PK_U8_I16_e64_gfx10
31064 { 15002, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #15002 = V_SAT_PK_U8_I16_e64_vi
31069 { 15007, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #15007 = V_SCREEN_PARTITION_4SE_B32_e32_vi
31070 { 15008, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #15008 = V_SCREEN_PARTITION_4SE_B32_e64_vi