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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18438 { 2376, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #2376 = V_BFREV_B32_dpp
19507 { 3445, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3445 = V_CVT_F16_I16_dpp
19511 { 3449, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3449 = V_CVT_F16_U16_dpp
19521 { 3459, 7, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3459 = V_CVT_F32_I32_dpp
19525 { 3463, 7, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3463 = V_CVT_F32_U32_dpp
19529 { 3467, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3467 = V_CVT_F32_UBYTE0_dpp
19533 { 3471, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3471 = V_CVT_F32_UBYTE1_dpp
19537 { 3475, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3475 = V_CVT_F32_UBYTE2_dpp
19541 { 3479, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3479 = V_CVT_F32_UBYTE3_dpp
19573 { 3511, 7, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3511 = V_CVT_OFF_F32_I4_dpp
19645 { 3583, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3583 = V_FFBH_I32_dpp
19649 { 3587, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3587 = V_FFBH_U32_dpp
19653 { 3591, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3591 = V_FFBL_B32_dpp
19927 { 3865, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3865 = V_MOV_B32_dpp
19934 { 3872, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3872 = V_MOV_FED_B32_dpp
19982 { 3920, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3920 = V_NOT_B32_dpp
20081 { 4019, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #4019 = V_SAT_PK_U8_I16_dpp
20085 { 4023, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #4023 = V_SCREEN_PARTITION_4SE_B32_dpp
28104 { 12042, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #12042 = V_BFREV_B32_dpp_vi
29770 { 13708, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #13708 = V_CVT_F16_I16_dpp_vi
29780 { 13718, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #13718 = V_CVT_F16_U16_dpp_vi
29808 { 13746, 7, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #13746 = V_CVT_F32_I32_dpp_vi
29820 { 13758, 7, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #13758 = V_CVT_F32_U32_dpp_vi
29832 { 13770, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #13770 = V_CVT_F32_UBYTE0_dpp_vi
29844 { 13782, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #13782 = V_CVT_F32_UBYTE1_dpp_vi
29856 { 13794, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #13794 = V_CVT_F32_UBYTE2_dpp_vi
29868 { 13806, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #13806 = V_CVT_F32_UBYTE3_dpp_vi
29958 { 13896, 7, 1, 8, 12, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #13896 = V_CVT_OFF_F32_I4_dpp_vi
30120 { 14058, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #14058 = V_FFBH_I32_dpp_vi
30132 { 14070, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #14070 = V_FFBH_U32_dpp_vi
30144 { 14082, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #14082 = V_FFBL_B32_dpp_vi
30711 { 14649, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #14649 = V_MOV_B32_dpp_vi
30723 { 14661, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #14661 = V_MOV_FED_B32_dpp_vi
30858 { 14796, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #14796 = V_NOT_B32_dpp_vi
31060 { 14998, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #14998 = V_SAT_PK_U8_I16_dpp_vi
31068 { 15006, 7, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #15006 = V_SCREEN_PARTITION_4SE_B32_dpp_gfx9