|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18405 { 2343, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2343 = V_ADD_U16_sdwa
18420 { 2358, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2358 = V_ASHRREV_I16_sdwa
19754 { 3692, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3692 = V_LSHLREV_B16_sdwa
19770 { 3708, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3708 = V_LSHRREV_B16_sdwa
19832 { 3770, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3770 = V_MAX_I16_sdwa
19844 { 3782, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3782 = V_MAX_U16_sdwa
19897 { 3835, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3835 = V_MIN_I16_sdwa
19909 { 3847, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3847 = V_MIN_U16_sdwa
19973 { 3911, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3911 = V_MUL_LO_U16_sdwa
20132 { 4070, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #4070 = V_SUBREV_U16_sdwa
20154 { 4092, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #4092 = V_SUB_U16_sdwa
28032 { 11970, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #11970 = V_ADD_U16_sdwa_gfx9
28033 { 11971, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #11971 = V_ADD_U16_sdwa_vi
28066 { 12004, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #12004 = V_ASHRREV_I16_sdwa_gfx9
28067 { 12005, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #12005 = V_ASHRREV_I16_sdwa_vi
30379 { 14317, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14317 = V_LSHLREV_B16_sdwa_gfx9
30380 { 14318, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14318 = V_LSHLREV_B16_sdwa_vi
30406 { 14344, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14344 = V_LSHRREV_B16_sdwa_gfx9
30407 { 14345, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14345 = V_LSHRREV_B16_sdwa_vi
30534 { 14472, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14472 = V_MAX_I16_sdwa_gfx9
30535 { 14473, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14473 = V_MAX_I16_sdwa_vi
30554 { 14492, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14492 = V_MAX_U16_sdwa_gfx9
30555 { 14493, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14493 = V_MAX_U16_sdwa_vi
30655 { 14593, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14593 = V_MIN_I16_sdwa_gfx9
30656 { 14594, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14594 = V_MIN_I16_sdwa_vi
30675 { 14613, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14613 = V_MIN_U16_sdwa_gfx9
30676 { 14614, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14614 = V_MIN_U16_sdwa_vi
30830 { 14768, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14768 = V_MUL_LO_U16_sdwa_gfx9
30831 { 14769, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #14769 = V_MUL_LO_U16_sdwa_vi
31190 { 15128, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #15128 = V_SUBREV_U16_sdwa_gfx9
31191 { 15129, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #15129 = V_SUBREV_U16_sdwa_vi
31253 { 15191, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #15191 = V_SUB_U16_sdwa_gfx9
31254 { 15192, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #15192 = V_SUB_U16_sdwa_vi