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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18403 { 2341, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2341 = V_ADD_U16_e32
18418 { 2356, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2356 = V_ASHRREV_I16_e32
19752 { 3690, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3690 = V_LSHLREV_B16_e32
19768 { 3706, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3706 = V_LSHRREV_B16_e32
19830 { 3768, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3768 = V_MAX_I16_e32
19842 { 3780, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3780 = V_MAX_U16_e32
19895 { 3833, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3833 = V_MIN_I16_e32
19907 { 3845, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3845 = V_MIN_U16_e32
19971 { 3909, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3909 = V_MUL_LO_U16_e32
20130 { 4068, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #4068 = V_SUBREV_U16_e32
20152 { 4090, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #4090 = V_SUB_U16_e32
28030 { 11968, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #11968 = V_ADD_U16_e32_vi
28063 { 12001, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #12001 = V_ASHRREV_I16_e32_vi
30376 { 14314, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #14314 = V_LSHLREV_B16_e32_vi
30403 { 14341, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #14341 = V_LSHRREV_B16_e32_vi
30531 { 14469, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #14469 = V_MAX_I16_e32_vi
30551 { 14489, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #14489 = V_MAX_U16_e32_vi
30652 { 14590, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #14590 = V_MIN_I16_e32_vi
30672 { 14610, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #14610 = V_MIN_U16_e32_vi
30827 { 14765, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #14765 = V_MUL_LO_U16_e32_vi
31188 { 15126, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #15126 = V_SUBREV_U16_e32_vi
31251 { 15189, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #15189 = V_SUB_U16_e32_vi