|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18399 { 2337, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2337 = V_ADD_I32_gfx9
18414 { 2352, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2352 = V_AND_B32_e64
18423 { 2361, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2361 = V_ASHRREV_I32_e64
18428 { 2366, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2366 = V_ASHR_I32_e64
18432 { 2370, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2370 = V_BCNT_U32_B32_e64
18437 { 2375, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2375 = V_BFM_B32_e64
19588 { 3526, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3526 = V_CVT_PK_I16_I32_e64
19590 { 3528, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3528 = V_CVT_PK_U16_U32_e64
19757 { 3695, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3695 = V_LSHLREV_B32_e64
19763 { 3701, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3701 = V_LSHL_B32_e64
19773 { 3711, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3711 = V_LSHRREV_B32_e64
19778 { 3716, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3716 = V_LSHR_B32_e64
19835 { 3773, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3773 = V_MAX_I32_e64
19847 { 3785, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3785 = V_MAX_U32_e64
19850 { 3788, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3788 = V_MBCNT_HI_U32_B32_e64
19852 { 3790, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3790 = V_MBCNT_LO_U32_B32_e64
19900 { 3838, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3838 = V_MIN_I32_e64
19912 { 3850, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3850 = V_MIN_U32_e64
19951 { 3889, 3, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3889 = V_MUL_HI_I32
19954 { 3892, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3892 = V_MUL_HI_I32_I24_e64
19956 { 3894, 3, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3894 = V_MUL_HI_U32
19959 { 3897, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3897 = V_MUL_HI_U32_U24_e64
19963 { 3901, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3901 = V_MUL_I32_I24_e64
19969 { 3907, 3, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3907 = V_MUL_LO_I32
19974 { 3912, 3, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3912 = V_MUL_LO_U32
19977 { 3915, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3915 = V_MUL_U32_U24_e64
19989 { 3927, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3927 = V_OR_B32_e64
20149 { 4087, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #4087 = V_SUB_I32_gfx9
20176 { 4114, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #4114 = V_XNOR_B32_e64
20181 { 4119, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #4119 = V_XOR_B32_e64
28018 { 11956, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #11956 = V_ADD_I32_gfx9_gfx9
28022 { 11960, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #11960 = V_ADD_NC_I32_gfx10
28054 { 11992, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #11992 = V_AND_B32_e64_gfx10
28055 { 11993, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #11993 = V_AND_B32_e64_gfx6_gfx7
28056 { 11994, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #11994 = V_AND_B32_e64_vi
28074 { 12012, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #12012 = V_ASHRREV_I32_e64_gfx10
28075 { 12013, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #12013 = V_ASHRREV_I32_e64_gfx6_gfx7
28076 { 12014, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #12014 = V_ASHRREV_I32_e64_vi
28083 { 12021, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #12021 = V_ASHR_I32_e64_gfx6_gfx7
28086 { 12024, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #12024 = V_BCNT_U32_B32_e64_gfx10
28087 { 12025, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #12025 = V_BCNT_U32_B32_e64_gfx6_gfx7
28088 { 12026, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #12026 = V_BCNT_U32_B32_e64_vi
28099 { 12037, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #12037 = V_BFM_B32_e64_gfx10
28100 { 12038, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #12038 = V_BFM_B32_e64_gfx6_gfx7
28101 { 12039, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #12039 = V_BFM_B32_e64_vi
29989 { 13927, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #13927 = V_CVT_PK_I16_I32_e64_gfx10
29990 { 13928, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #13928 = V_CVT_PK_I16_I32_e64_gfx6_gfx7
29991 { 13929, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #13929 = V_CVT_PK_I16_I32_e64_vi
29993 { 13931, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #13931 = V_CVT_PK_U16_U32_e64_gfx10
29994 { 13932, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #13932 = V_CVT_PK_U16_U32_e64_gfx6_gfx7
29995 { 13933, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #13933 = V_CVT_PK_U16_U32_e64_vi
30387 { 14325, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14325 = V_LSHLREV_B32_e64_gfx10
30388 { 14326, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14326 = V_LSHLREV_B32_e64_gfx6_gfx7
30389 { 14327, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14327 = V_LSHLREV_B32_e64_vi
30398 { 14336, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14336 = V_LSHL_B32_e64_gfx6_gfx7
30414 { 14352, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14352 = V_LSHRREV_B32_e64_gfx10
30415 { 14353, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14353 = V_LSHRREV_B32_e64_gfx6_gfx7
30416 { 14354, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14354 = V_LSHRREV_B32_e64_vi
30423 { 14361, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14361 = V_LSHR_B32_e64_gfx6_gfx7
30542 { 14480, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14480 = V_MAX_I32_e64_gfx10
30543 { 14481, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14481 = V_MAX_I32_e64_gfx6_gfx7
30544 { 14482, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14482 = V_MAX_I32_e64_vi
30562 { 14500, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14500 = V_MAX_U32_e64_gfx10
30563 { 14501, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14501 = V_MAX_U32_e64_gfx6_gfx7
30564 { 14502, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14502 = V_MAX_U32_e64_vi
30569 { 14507, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14507 = V_MBCNT_HI_U32_B32_e64_gfx10
30570 { 14508, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14508 = V_MBCNT_HI_U32_B32_e64_gfx6_gfx7
30571 { 14509, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14509 = V_MBCNT_HI_U32_B32_e64_vi
30573 { 14511, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14511 = V_MBCNT_LO_U32_B32_e64_gfx10
30574 { 14512, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14512 = V_MBCNT_LO_U32_B32_e64_gfx6_gfx7
30575 { 14513, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14513 = V_MBCNT_LO_U32_B32_e64_vi
30663 { 14601, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14601 = V_MIN_I32_e64_gfx10
30664 { 14602, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14602 = V_MIN_I32_e64_gfx6_gfx7
30665 { 14603, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14603 = V_MIN_I32_e64_vi
30683 { 14621, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14621 = V_MIN_U32_e64_gfx10
30684 { 14622, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14622 = V_MIN_U32_e64_gfx6_gfx7
30685 { 14623, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14623 = V_MIN_U32_e64_vi
30775 { 14713, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14713 = V_MUL_HI_I32_I24_e64_gfx10
30776 { 14714, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14714 = V_MUL_HI_I32_I24_e64_gfx6_gfx7
30777 { 14715, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14715 = V_MUL_HI_I32_I24_e64_vi
30781 { 14719, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14719 = V_MUL_HI_I32_gfx10
30782 { 14720, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14720 = V_MUL_HI_I32_gfx6_gfx7
30783 { 14721, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14721 = V_MUL_HI_I32_vi
30790 { 14728, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14728 = V_MUL_HI_U32_U24_e64_gfx10
30791 { 14729, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14729 = V_MUL_HI_U32_U24_e64_gfx6_gfx7
30792 { 14730, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14730 = V_MUL_HI_U32_U24_e64_vi
30796 { 14734, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14734 = V_MUL_HI_U32_gfx10
30797 { 14735, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14735 = V_MUL_HI_U32_gfx6_gfx7
30798 { 14736, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14736 = V_MUL_HI_U32_vi
30805 { 14743, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14743 = V_MUL_I32_I24_e64_gfx10
30806 { 14744, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14744 = V_MUL_I32_I24_e64_gfx6_gfx7
30807 { 14745, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14745 = V_MUL_I32_I24_e64_vi
30823 { 14761, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14761 = V_MUL_LO_I32_gfx10
30824 { 14762, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14762 = V_MUL_LO_I32_gfx6_gfx7
30825 { 14763, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14763 = V_MUL_LO_I32_vi
30832 { 14770, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14770 = V_MUL_LO_U32_gfx10
30833 { 14771, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14771 = V_MUL_LO_U32_gfx6_gfx7
30834 { 14772, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14772 = V_MUL_LO_U32_vi
30841 { 14779, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14779 = V_MUL_U32_U24_e64_gfx10
30842 { 14780, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14780 = V_MUL_U32_U24_e64_gfx6_gfx7
30843 { 14781, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14781 = V_MUL_U32_U24_e64_vi
30876 { 14814, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14814 = V_OR_B32_e64_gfx10
30877 { 14815, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14815 = V_OR_B32_e64_gfx6_gfx7
30878 { 14816, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #14816 = V_OR_B32_e64_vi
31241 { 15179, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #15179 = V_SUB_I32_gfx9_gfx9
31243 { 15181, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #15181 = V_SUB_NC_I32_gfx10
31307 { 15245, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #15245 = V_XNOR_B32_e64_gfx10
31308 { 15246, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #15246 = V_XNOR_B32_e64_vi
31319 { 15257, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #15257 = V_XOR_B32_e64_gfx10
31320 { 15258, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #15258 = V_XOR_B32_e64_gfx6_gfx7
31321 { 15259, 3, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #15259 = V_XOR_B32_e64_vi