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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18392 { 2330, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2330 = V_ADD_F32_e64
19586 { 3524, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x1a00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3524 = V_CVT_PKRTZ_F16_F32_e64
19791 { 3729, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3729 = V_MAC_LEGACY_F32_e64
19826 { 3764, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3764 = V_MAX_F32_e64
19839 { 3777, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3777 = V_MAX_LEGACY_F32_e64
19891 { 3829, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3829 = V_MIN_F32_e64
19904 { 3842, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3842 = V_MIN_LEGACY_F32_e64
19948 { 3886, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3886 = V_MUL_F32_e64
19967 { 3905, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3905 = V_MUL_LEGACY_F32_e64
20123 { 4061, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #4061 = V_SUBREV_F32_e64
20143 { 4081, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #4081 = V_SUB_F32_e64
28006 { 11944, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #11944 = V_ADD_F32_e64_gfx10
28007 { 11945, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #11945 = V_ADD_F32_e64_gfx6_gfx7
28008 { 11946, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #11946 = V_ADD_F32_e64_vi
29985 { 13923, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1a00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #13923 = V_CVT_PKRTZ_F16_F32_e64_gfx10
29986 { 13924, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1a00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #13924 = V_CVT_PKRTZ_F16_F32_e64_gfx6_gfx7
29987 { 13925, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1a00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #13925 = V_CVT_PKRTZ_F16_F32_e64_vi
30443 { 14381, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14381 = V_MAC_LEGACY_F32_e64_gfx10
30444 { 14382, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14382 = V_MAC_LEGACY_F32_e64_gfx6_gfx7
30521 { 14459, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14459 = V_MAX_F32_e64_gfx10
30522 { 14460, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14460 = V_MAX_F32_e64_gfx6_gfx7
30523 { 14461, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14461 = V_MAX_F32_e64_vi
30549 { 14487, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14487 = V_MAX_LEGACY_F32_e64_gfx6_gfx7
30642 { 14580, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14580 = V_MIN_F32_e64_gfx10
30643 { 14581, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14581 = V_MIN_F32_e64_gfx6_gfx7
30644 { 14582, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14582 = V_MIN_F32_e64_vi
30670 { 14608, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14608 = V_MIN_LEGACY_F32_e64_gfx6_gfx7
30760 { 14698, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14698 = V_MUL_F32_e64_gfx10
30761 { 14699, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14699 = V_MUL_F32_e64_gfx6_gfx7
30762 { 14700, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14700 = V_MUL_F32_e64_vi
30817 { 14755, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14755 = V_MUL_LEGACY_F32_e64_gfx10
30818 { 14756, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14756 = V_MUL_LEGACY_F32_e64_gfx6_gfx7
30819 { 14757, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #14757 = V_MUL_LEGACY_F32_e64_vi
31174 { 15112, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #15112 = V_SUBREV_F32_e64_gfx10
31175 { 15113, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #15113 = V_SUBREV_F32_e64_gfx6_gfx7
31176 { 15114, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #15114 = V_SUBREV_F32_e64_vi
31232 { 15170, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #15170 = V_SUB_F32_e64_gfx10
31233 { 15171, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #15171 = V_SUB_F32_e64_gfx6_gfx7
31234 { 15172, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #15172 = V_SUB_F32_e64_vi