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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18391 { 2329, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2329 = V_ADD_F32_e32
19577 { 3515, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3515 = V_CVT_PKACCUM_U8_F32_e32
19580 { 3518, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3518 = V_CVT_PKNORM_I16_F32_e32
19583 { 3521, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3521 = V_CVT_PKNORM_U16_F32_e32
19585 { 3523, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3523 = V_CVT_PKRTZ_F16_F32_e32
19731 { 3669, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3669 = V_LDEXP_F32_e32
19790 { 3728, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3728 = V_MAC_LEGACY_F32_e32
19825 { 3763, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3763 = V_MAX_F32_e32
19838 { 3776, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3776 = V_MAX_LEGACY_F32_e32
19890 { 3828, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3828 = V_MIN_F32_e32
19903 { 3841, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3841 = V_MIN_LEGACY_F32_e32
19947 { 3885, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3885 = V_MUL_F32_e32
19966 { 3904, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3904 = V_MUL_LEGACY_F32_e32
20122 { 4060, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #4060 = V_SUBREV_F32_e32
20142 { 4080, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #4080 = V_SUB_F32_e32
28003 { 11941, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #11941 = V_ADD_F32_e32_gfx10
28004 { 11942, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #11942 = V_ADD_F32_e32_gfx6_gfx7
28005 { 11943, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #11943 = V_ADD_F32_e32_vi
29968 { 13906, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #13906 = V_CVT_PKACCUM_U8_F32_e32_gfx6_gfx7
29973 { 13911, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #13911 = V_CVT_PKNORM_I16_F32_e32_gfx6_gfx7
29979 { 13917, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #13917 = V_CVT_PKNORM_U16_F32_e32_gfx6_gfx7
29983 { 13921, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #13921 = V_CVT_PKRTZ_F16_F32_e32_gfx10
29984 { 13922, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #13922 = V_CVT_PKRTZ_F16_F32_e32_gfx6_gfx7
30334 { 14272, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14272 = V_LDEXP_F32_e32_gfx6_gfx7
30441 { 14379, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14379 = V_MAC_LEGACY_F32_e32_gfx10
30442 { 14380, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14380 = V_MAC_LEGACY_F32_e32_gfx6_gfx7
30518 { 14456, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14456 = V_MAX_F32_e32_gfx10
30519 { 14457, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14457 = V_MAX_F32_e32_gfx6_gfx7
30520 { 14458, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14458 = V_MAX_F32_e32_vi
30548 { 14486, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14486 = V_MAX_LEGACY_F32_e32_gfx6_gfx7
30639 { 14577, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14577 = V_MIN_F32_e32_gfx10
30640 { 14578, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14578 = V_MIN_F32_e32_gfx6_gfx7
30641 { 14579, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14579 = V_MIN_F32_e32_vi
30669 { 14607, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14607 = V_MIN_LEGACY_F32_e32_gfx6_gfx7
30757 { 14695, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14695 = V_MUL_F32_e32_gfx10
30758 { 14696, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14696 = V_MUL_F32_e32_gfx6_gfx7
30759 { 14697, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14697 = V_MUL_F32_e32_vi
30814 { 14752, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14752 = V_MUL_LEGACY_F32_e32_gfx10
30815 { 14753, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14753 = V_MUL_LEGACY_F32_e32_gfx6_gfx7
30816 { 14754, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #14754 = V_MUL_LEGACY_F32_e32_vi
31171 { 15109, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #15109 = V_SUBREV_F32_e32_gfx10
31172 { 15110, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #15110 = V_SUBREV_F32_e32_gfx6_gfx7
31173 { 15111, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #15111 = V_SUBREV_F32_e32_vi
31229 { 15167, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #15167 = V_SUB_F32_e32_gfx10
31230 { 15168, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #15168 = V_SUB_F32_e32_gfx6_gfx7
31231 { 15169, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #15169 = V_SUB_F32_e32_vi