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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18388 { 2326, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2326 = V_ADD_F16_e64
19579 { 3517, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3517 = V_CVT_PKNORM_I16_F16
19582 { 3520, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3520 = V_CVT_PKNORM_U16_F16
19822 { 3760, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3760 = V_MAX_F16_e64
19887 { 3825, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3825 = V_MIN_F16_e64
19944 { 3882, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3882 = V_MUL_F16_e64
19991 { 3929, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3929 = V_PACK_B32_F16
20119 { 4057, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #4057 = V_SUBREV_F16_e64
20139 { 4077, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #4077 = V_SUB_F16_e64
27995 { 11933, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #11933 = V_ADD_F16_e64_gfx10
27996 { 11934, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #11934 = V_ADD_F16_e64_vi
29971 { 13909, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #13909 = V_CVT_PKNORM_I16_F16_gfx10
29972 { 13910, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #13910 = V_CVT_PKNORM_I16_F16_vi
29977 { 13915, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #13915 = V_CVT_PKNORM_U16_F16_gfx10
29978 { 13916, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #13916 = V_CVT_PKNORM_U16_F16_vi
30510 { 14448, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #14448 = V_MAX_F16_e64_gfx10
30511 { 14449, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #14449 = V_MAX_F16_e64_vi
30631 { 14569, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #14569 = V_MIN_F16_e64_gfx10
30632 { 14570, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #14570 = V_MIN_F16_e64_vi
30749 { 14687, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #14687 = V_MUL_F16_e64_gfx10
30750 { 14688, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #14688 = V_MUL_F16_e64_vi
30882 { 14820, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #14820 = V_PACK_B32_F16_gfx10
30883 { 14821, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #14821 = V_PACK_B32_F16_vi
31163 { 15101, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #15101 = V_SUBREV_F16_e64_gfx10
31164 { 15102, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #15102 = V_SUBREV_F16_e64_vi
31221 { 15159, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #15159 = V_SUB_F16_e64_gfx10
31222 { 15160, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #15160 = V_SUB_F16_e64_vi