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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18387 { 2325, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2325 = V_ADD_F16_e32
19728 { 3666, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3666 = V_LDEXP_F16_e32
19821 { 3759, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3759 = V_MAX_F16_e32
19886 { 3824, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3824 = V_MIN_F16_e32
19943 { 3881, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3881 = V_MUL_F16_e32
20118 { 4056, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #4056 = V_SUBREV_F16_e32
20138 { 4076, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #4076 = V_SUB_F16_e32
27993 { 11931, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #11931 = V_ADD_F16_e32_gfx10
27994 { 11932, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #11932 = V_ADD_F16_e32_vi
30327 { 14265, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #14265 = V_LDEXP_F16_e32_gfx10
30328 { 14266, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #14266 = V_LDEXP_F16_e32_vi
30508 { 14446, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #14446 = V_MAX_F16_e32_gfx10
30509 { 14447, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #14447 = V_MAX_F16_e32_vi
30629 { 14567, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #14567 = V_MIN_F16_e32_gfx10
30630 { 14568, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #14568 = V_MIN_F16_e32_vi
30747 { 14685, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #14685 = V_MUL_F16_e32_gfx10
30748 { 14686, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #14686 = V_MUL_F16_e32_vi
31161 { 15099, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #15099 = V_SUBREV_F16_e32_gfx10
31162 { 15100, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #15100 = V_SUBREV_F16_e32_vi
31219 { 15157, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #15157 = V_SUB_F16_e32_gfx10
31220 { 15158, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #15158 = V_SUB_F16_e32_vi