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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18386 { 2324, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2324 = V_ADD_F16_dpp
18390 { 2328, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2328 = V_ADD_F32_dpp
19486 { 3424, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList13, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3424 = V_CNDMASK_B32_dpp
19727 { 3665, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3665 = V_LDEXP_F16_dpp
19789 { 3727, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3727 = V_MAC_LEGACY_F32_dpp
19820 { 3758, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3758 = V_MAX_F16_dpp
19824 { 3762, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3762 = V_MAX_F32_dpp
19837 { 3775, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3775 = V_MAX_LEGACY_F32_dpp
19885 { 3823, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3823 = V_MIN_F16_dpp
19889 { 3827, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3827 = V_MIN_F32_dpp
19902 { 3840, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3840 = V_MIN_LEGACY_F32_dpp
19942 { 3880, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3880 = V_MUL_F16_dpp
19946 { 3884, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3884 = V_MUL_F32_dpp
19965 { 3903, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3903 = V_MUL_LEGACY_F32_dpp
20002 { 3940, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3940 = V_PK_FMAC_F16_dpp
20117 { 4055, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #4055 = V_SUBREV_F16_dpp
20121 { 4059, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #4059 = V_SUBREV_F32_dpp
20137 { 4075, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #4075 = V_SUB_F16_dpp
20141 { 4079, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #4079 = V_SUB_F32_dpp
27992 { 11930, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #11930 = V_ADD_F16_dpp_vi
28002 { 11940, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #11940 = V_ADD_F32_dpp_vi
29708 { 13646, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList13, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #13646 = V_CNDMASK_B32_dpp_vi
30326 { 14264, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #14264 = V_LDEXP_F16_dpp_vi
30507 { 14445, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #14445 = V_MAX_F16_dpp_vi
30517 { 14455, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #14455 = V_MAX_F32_dpp_vi
30628 { 14566, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #14566 = V_MIN_F16_dpp_vi
30638 { 14576, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #14576 = V_MIN_F32_dpp_vi
30746 { 14684, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #14684 = V_MUL_F16_dpp_vi
30756 { 14694, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #14694 = V_MUL_F32_dpp_vi
30813 { 14751, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #14751 = V_MUL_LEGACY_F32_dpp_vi
31160 { 15098, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #15098 = V_SUBREV_F16_dpp_vi
31170 { 15108, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #15108 = V_SUBREV_F32_dpp_vi
31218 { 15156, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #15156 = V_SUB_F16_dpp_vi
31228 { 15166, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #15166 = V_SUB_F32_dpp_vi