|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18385 { 2323, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #2323 = V_ADDC_U32_sdwa
18400 { 2338, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #2338 = V_ADD_I32_sdwa
18409 { 2347, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2347 = V_ADD_U32_sdwa
18415 { 2353, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2353 = V_AND_B32_sdwa
18424 { 2362, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2362 = V_ASHRREV_I32_sdwa
18429 { 2367, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2367 = V_ASHR_I32_sdwa
19489 { 3427, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3427 = V_CNDMASK_B32_sdwa
19758 { 3696, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3696 = V_LSHLREV_B32_sdwa
19764 { 3702, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3702 = V_LSHL_B32_sdwa
19774 { 3712, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3712 = V_LSHRREV_B32_sdwa
19779 { 3717, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3717 = V_LSHR_B32_sdwa
19836 { 3774, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3774 = V_MAX_I32_sdwa
19848 { 3786, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3786 = V_MAX_U32_sdwa
19901 { 3839, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3839 = V_MIN_I32_sdwa
19913 { 3851, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3851 = V_MIN_U32_sdwa
19955 { 3893, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3893 = V_MUL_HI_I32_I24_sdwa
19960 { 3898, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3898 = V_MUL_HI_U32_U24_sdwa
19964 { 3902, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3902 = V_MUL_I32_I24_sdwa
19978 { 3916, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3916 = V_MUL_U32_U24_sdwa
19990 { 3928, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3928 = V_OR_B32_sdwa
20112 { 4050, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #4050 = V_SUBBREV_U32_sdwa
20116 { 4054, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #4054 = V_SUBB_U32_sdwa
20128 { 4066, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #4066 = V_SUBREV_I32_sdwa
20136 { 4074, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #4074 = V_SUBREV_U32_sdwa
20150 { 4088, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #4088 = V_SUB_I32_sdwa
20158 { 4096, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #4096 = V_SUB_U32_sdwa
20177 { 4115, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #4115 = V_XNOR_B32_sdwa
20182 { 4120, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #4120 = V_XOR_B32_sdwa
27967 { 11905, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #11905 = V_ADDC_CO_U32_sdwa_gfx9
27973 { 11911, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #11911 = V_ADDC_U32_sdwa_vi
27982 { 11920, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #11920 = V_ADD_CO_CI_U32_sdwa_gfx10
27983 { 11921, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #11921 = V_ADD_CO_CI_U32_sdwa_w32_gfx10
27984 { 11922, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #11922 = V_ADD_CO_CI_U32_sdwa_w64_gfx10
27989 { 11927, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #11927 = V_ADD_CO_U32_sdwa_gfx9
28028 { 11966, 10, 1, 8, 2, 0, 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #11966 = V_ADD_NC_U32_sdwa_gfx10
28040 { 11978, 10, 1, 8, 2, 0, 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #11978 = V_ADD_U32_sdwa_gfx9
28041 { 11979, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #11979 = V_ADD_U32_sdwa_vi
28057 { 11995, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #11995 = V_AND_B32_sdwa_gfx10
28058 { 11996, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #11996 = V_AND_B32_sdwa_gfx9
28059 { 11997, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #11997 = V_AND_B32_sdwa_vi
28077 { 12015, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #12015 = V_ASHRREV_I32_sdwa_gfx10
28078 { 12016, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #12016 = V_ASHRREV_I32_sdwa_gfx9
28079 { 12017, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #12017 = V_ASHRREV_I32_sdwa_vi
29717 { 13655, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #13655 = V_CNDMASK_B32_sdwa_gfx10
29718 { 13656, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #13656 = V_CNDMASK_B32_sdwa_gfx9
29719 { 13657, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #13657 = V_CNDMASK_B32_sdwa_vi
29720 { 13658, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #13658 = V_CNDMASK_B32_sdwa_w32_gfx10
29721 { 13659, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #13659 = V_CNDMASK_B32_sdwa_w64_gfx10
30390 { 14328, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14328 = V_LSHLREV_B32_sdwa_gfx10
30391 { 14329, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14329 = V_LSHLREV_B32_sdwa_gfx9
30392 { 14330, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14330 = V_LSHLREV_B32_sdwa_vi
30417 { 14355, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14355 = V_LSHRREV_B32_sdwa_gfx10
30418 { 14356, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14356 = V_LSHRREV_B32_sdwa_gfx9
30419 { 14357, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14357 = V_LSHRREV_B32_sdwa_vi
30545 { 14483, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14483 = V_MAX_I32_sdwa_gfx10
30546 { 14484, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14484 = V_MAX_I32_sdwa_gfx9
30547 { 14485, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14485 = V_MAX_I32_sdwa_vi
30565 { 14503, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14503 = V_MAX_U32_sdwa_gfx10
30566 { 14504, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14504 = V_MAX_U32_sdwa_gfx9
30567 { 14505, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14505 = V_MAX_U32_sdwa_vi
30666 { 14604, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14604 = V_MIN_I32_sdwa_gfx10
30667 { 14605, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14605 = V_MIN_I32_sdwa_gfx9
30668 { 14606, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14606 = V_MIN_I32_sdwa_vi
30686 { 14624, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14624 = V_MIN_U32_sdwa_gfx10
30687 { 14625, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14625 = V_MIN_U32_sdwa_gfx9
30688 { 14626, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14626 = V_MIN_U32_sdwa_vi
30778 { 14716, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14716 = V_MUL_HI_I32_I24_sdwa_gfx10
30779 { 14717, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14717 = V_MUL_HI_I32_I24_sdwa_gfx9
30780 { 14718, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14718 = V_MUL_HI_I32_I24_sdwa_vi
30793 { 14731, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14731 = V_MUL_HI_U32_U24_sdwa_gfx10
30794 { 14732, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14732 = V_MUL_HI_U32_U24_sdwa_gfx9
30795 { 14733, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14733 = V_MUL_HI_U32_U24_sdwa_vi
30808 { 14746, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14746 = V_MUL_I32_I24_sdwa_gfx10
30809 { 14747, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14747 = V_MUL_I32_I24_sdwa_gfx9
30810 { 14748, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14748 = V_MUL_I32_I24_sdwa_vi
30844 { 14782, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14782 = V_MUL_U32_U24_sdwa_gfx10
30845 { 14783, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14783 = V_MUL_U32_U24_sdwa_gfx9
30846 { 14784, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14784 = V_MUL_U32_U24_sdwa_vi
30879 { 14817, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14817 = V_OR_B32_sdwa_gfx10
30880 { 14818, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14818 = V_OR_B32_sdwa_gfx9
30881 { 14819, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #14819 = V_OR_B32_sdwa_vi
31125 { 15063, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15063 = V_SUBBREV_CO_U32_sdwa_gfx9
31131 { 15069, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15069 = V_SUBBREV_U32_sdwa_vi
31135 { 15073, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15073 = V_SUBB_CO_U32_sdwa_gfx9
31141 { 15079, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15079 = V_SUBB_U32_sdwa_vi
31150 { 15088, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15088 = V_SUBREV_CO_CI_U32_sdwa_gfx10
31151 { 15089, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15089 = V_SUBREV_CO_CI_U32_sdwa_w32_gfx10
31152 { 15090, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15090 = V_SUBREV_CO_CI_U32_sdwa_w64_gfx10
31157 { 15095, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15095 = V_SUBREV_CO_U32_sdwa_gfx9
31186 { 15124, 10, 1, 8, 2, 0, 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #15124 = V_SUBREV_NC_U32_sdwa_gfx10
31198 { 15136, 10, 1, 8, 2, 0, 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #15136 = V_SUBREV_U32_sdwa_gfx9
31199 { 15137, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15137 = V_SUBREV_U32_sdwa_vi
31208 { 15146, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15146 = V_SUB_CO_CI_U32_sdwa_gfx10
31209 { 15147, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15147 = V_SUB_CO_CI_U32_sdwa_w32_gfx10
31210 { 15148, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15148 = V_SUB_CO_CI_U32_sdwa_w64_gfx10
31215 { 15153, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15153 = V_SUB_CO_U32_sdwa_gfx9
31249 { 15187, 10, 1, 8, 2, 0, 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #15187 = V_SUB_NC_U32_sdwa_gfx10
31261 { 15199, 10, 1, 8, 2, 0, 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #15199 = V_SUB_U32_sdwa_gfx9
31262 { 15200, 10, 1, 8, 9, 0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #15200 = V_SUB_U32_sdwa_vi
31309 { 15247, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #15247 = V_XNOR_B32_sdwa_gfx10
31310 { 15248, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #15248 = V_XNOR_B32_sdwa_gfx9
31311 { 15249, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #15249 = V_XNOR_B32_sdwa_vi
31322 { 15260, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #15260 = V_XOR_B32_sdwa_gfx10
31323 { 15261, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #15261 = V_XOR_B32_sdwa_gfx9
31324 { 15262, 10, 1, 8, 2, 0, 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #15262 = V_XOR_B32_sdwa_vi