|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18383 { 2321, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #2321 = V_ADDC_U32_e32
18397 { 2335, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #2335 = V_ADD_I32_e32
18407 { 2345, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2345 = V_ADD_U32_e32
18413 { 2351, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2351 = V_AND_B32_e32
18422 { 2360, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2360 = V_ASHRREV_I32_e32
18427 { 2365, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2365 = V_ASHR_I32_e32
18431 { 2369, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2369 = V_BCNT_U32_B32_e32
18436 { 2374, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2374 = V_BFM_B32_e32
19487 { 3425, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList13, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3425 = V_CNDMASK_B32_e32
19587 { 3525, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3525 = V_CVT_PK_I16_I32_e32
19589 { 3527, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3527 = V_CVT_PK_U16_U32_e32
19756 { 3694, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3694 = V_LSHLREV_B32_e32
19762 { 3700, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3700 = V_LSHL_B32_e32
19772 { 3710, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3710 = V_LSHRREV_B32_e32
19777 { 3715, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3715 = V_LSHR_B32_e32
19834 { 3772, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3772 = V_MAX_I32_e32
19846 { 3784, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3784 = V_MAX_U32_e32
19849 { 3787, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3787 = V_MBCNT_HI_U32_B32_e32
19851 { 3789, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3789 = V_MBCNT_LO_U32_B32_e32
19899 { 3837, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3837 = V_MIN_I32_e32
19911 { 3849, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3849 = V_MIN_U32_e32
19953 { 3891, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3891 = V_MUL_HI_I32_I24_e32
19958 { 3896, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3896 = V_MUL_HI_U32_U24_e32
19962 { 3900, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3900 = V_MUL_I32_I24_e32
19976 { 3914, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3914 = V_MUL_U32_U24_e32
19988 { 3926, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3926 = V_OR_B32_e32
20110 { 4048, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #4048 = V_SUBBREV_U32_e32
20114 { 4052, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #4052 = V_SUBB_U32_e32
20126 { 4064, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #4064 = V_SUBREV_I32_e32
20134 { 4072, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #4072 = V_SUBREV_U32_e32
20147 { 4085, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #4085 = V_SUB_I32_e32
20156 { 4094, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #4094 = V_SUB_U32_e32
20175 { 4113, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #4113 = V_XNOR_B32_e32
20180 { 4118, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #4118 = V_XOR_B32_e32
27965 { 11903, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #11903 = V_ADDC_CO_U32_e32_gfx9
27969 { 11907, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #11907 = V_ADDC_U32_e32_gfx6_gfx7
27970 { 11908, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #11908 = V_ADDC_U32_e32_vi
27980 { 11918, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #11918 = V_ADD_CO_CI_U32_e32_gfx10
27986 { 11924, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #11924 = V_ADD_CO_U32_e32_gfx9
28016 { 11954, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #11954 = V_ADD_I32_e32_gfx6_gfx7
28026 { 11964, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #11964 = V_ADD_NC_U32_e32_gfx10
28036 { 11974, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #11974 = V_ADD_U32_e32_gfx9
28037 { 11975, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #11975 = V_ADD_U32_e32_vi
28051 { 11989, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #11989 = V_AND_B32_e32_gfx10
28052 { 11990, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #11990 = V_AND_B32_e32_gfx6_gfx7
28053 { 11991, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #11991 = V_AND_B32_e32_vi
28071 { 12009, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #12009 = V_ASHRREV_I32_e32_gfx10
28072 { 12010, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #12010 = V_ASHRREV_I32_e32_gfx6_gfx7
28073 { 12011, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #12011 = V_ASHRREV_I32_e32_vi
28082 { 12020, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #12020 = V_ASHR_I32_e32_gfx6_gfx7
28085 { 12023, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #12023 = V_BCNT_U32_B32_e32_gfx6_gfx7
28098 { 12036, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #12036 = V_BFM_B32_e32_gfx6_gfx7
29711 { 13649, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList13, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #13649 = V_CNDMASK_B32_e32_gfx10
29712 { 13650, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList13, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #13650 = V_CNDMASK_B32_e32_gfx6_gfx7
29713 { 13651, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList13, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #13651 = V_CNDMASK_B32_e32_vi
29988 { 13926, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #13926 = V_CVT_PK_I16_I32_e32_gfx6_gfx7
29992 { 13930, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #13930 = V_CVT_PK_U16_U32_e32_gfx6_gfx7
30384 { 14322, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14322 = V_LSHLREV_B32_e32_gfx10
30385 { 14323, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14323 = V_LSHLREV_B32_e32_gfx6_gfx7
30386 { 14324, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14324 = V_LSHLREV_B32_e32_vi
30397 { 14335, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14335 = V_LSHL_B32_e32_gfx6_gfx7
30411 { 14349, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14349 = V_LSHRREV_B32_e32_gfx10
30412 { 14350, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14350 = V_LSHRREV_B32_e32_gfx6_gfx7
30413 { 14351, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14351 = V_LSHRREV_B32_e32_vi
30422 { 14360, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14360 = V_LSHR_B32_e32_gfx6_gfx7
30539 { 14477, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14477 = V_MAX_I32_e32_gfx10
30540 { 14478, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14478 = V_MAX_I32_e32_gfx6_gfx7
30541 { 14479, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14479 = V_MAX_I32_e32_vi
30559 { 14497, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14497 = V_MAX_U32_e32_gfx10
30560 { 14498, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14498 = V_MAX_U32_e32_gfx6_gfx7
30561 { 14499, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14499 = V_MAX_U32_e32_vi
30568 { 14506, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14506 = V_MBCNT_HI_U32_B32_e32_gfx6_gfx7
30572 { 14510, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14510 = V_MBCNT_LO_U32_B32_e32_gfx6_gfx7
30660 { 14598, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14598 = V_MIN_I32_e32_gfx10
30661 { 14599, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14599 = V_MIN_I32_e32_gfx6_gfx7
30662 { 14600, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14600 = V_MIN_I32_e32_vi
30680 { 14618, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14618 = V_MIN_U32_e32_gfx10
30681 { 14619, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14619 = V_MIN_U32_e32_gfx6_gfx7
30682 { 14620, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14620 = V_MIN_U32_e32_vi
30772 { 14710, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14710 = V_MUL_HI_I32_I24_e32_gfx10
30773 { 14711, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14711 = V_MUL_HI_I32_I24_e32_gfx6_gfx7
30774 { 14712, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14712 = V_MUL_HI_I32_I24_e32_vi
30787 { 14725, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14725 = V_MUL_HI_U32_U24_e32_gfx10
30788 { 14726, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14726 = V_MUL_HI_U32_U24_e32_gfx6_gfx7
30789 { 14727, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14727 = V_MUL_HI_U32_U24_e32_vi
30802 { 14740, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14740 = V_MUL_I32_I24_e32_gfx10
30803 { 14741, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14741 = V_MUL_I32_I24_e32_gfx6_gfx7
30804 { 14742, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14742 = V_MUL_I32_I24_e32_vi
30838 { 14776, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14776 = V_MUL_U32_U24_e32_gfx10
30839 { 14777, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14777 = V_MUL_U32_U24_e32_gfx6_gfx7
30840 { 14778, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14778 = V_MUL_U32_U24_e32_vi
30873 { 14811, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14811 = V_OR_B32_e32_gfx10
30874 { 14812, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14812 = V_OR_B32_e32_gfx6_gfx7
30875 { 14813, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #14813 = V_OR_B32_e32_vi
31123 { 15061, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15061 = V_SUBBREV_CO_U32_e32_gfx9
31127 { 15065, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15065 = V_SUBBREV_U32_e32_gfx6_gfx7
31128 { 15066, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15066 = V_SUBBREV_U32_e32_vi
31133 { 15071, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15071 = V_SUBB_CO_U32_e32_gfx9
31137 { 15075, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15075 = V_SUBB_U32_e32_gfx6_gfx7
31138 { 15076, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15076 = V_SUBB_U32_e32_vi
31148 { 15086, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15086 = V_SUBREV_CO_CI_U32_e32_gfx10
31154 { 15092, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15092 = V_SUBREV_CO_U32_e32_gfx9
31180 { 15118, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15118 = V_SUBREV_I32_e32_gfx6_gfx7
31184 { 15122, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #15122 = V_SUBREV_NC_U32_e32_gfx10
31194 { 15132, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #15132 = V_SUBREV_U32_e32_gfx9
31195 { 15133, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15133 = V_SUBREV_U32_e32_vi
31206 { 15144, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15144 = V_SUB_CO_CI_U32_e32_gfx10
31212 { 15150, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15150 = V_SUB_CO_U32_e32_gfx9
31239 { 15177, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15177 = V_SUB_I32_e32_gfx6_gfx7
31247 { 15185, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #15185 = V_SUB_NC_U32_e32_gfx10
31257 { 15195, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #15195 = V_SUB_U32_e32_gfx9
31258 { 15196, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #15196 = V_SUB_U32_e32_vi
31305 { 15243, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #15243 = V_XNOR_B32_e32_gfx10
31306 { 15244, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #15244 = V_XNOR_B32_e32_vi
31316 { 15254, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #15254 = V_XOR_B32_e32_gfx10
31317 { 15255, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #15255 = V_XOR_B32_e32_gfx6_gfx7
31318 { 15256, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #15256 = V_XOR_B32_e32_vi