|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18382 { 2320, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #2320 = V_ADDC_U32_dpp
18396 { 2334, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #2334 = V_ADD_I32_dpp
18402 { 2340, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2340 = V_ADD_U16_dpp
18406 { 2344, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2344 = V_ADD_U32_dpp
18412 { 2350, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2350 = V_AND_B32_dpp
18417 { 2355, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2355 = V_ASHRREV_I16_dpp
18421 { 2359, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2359 = V_ASHRREV_I32_dpp
18426 { 2364, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2364 = V_ASHR_I32_dpp
19751 { 3689, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3689 = V_LSHLREV_B16_dpp
19755 { 3693, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3693 = V_LSHLREV_B32_dpp
19761 { 3699, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3699 = V_LSHL_B32_dpp
19767 { 3705, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3705 = V_LSHRREV_B16_dpp
19771 { 3709, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3709 = V_LSHRREV_B32_dpp
19776 { 3714, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3714 = V_LSHR_B32_dpp
19829 { 3767, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3767 = V_MAX_I16_dpp
19833 { 3771, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3771 = V_MAX_I32_dpp
19841 { 3779, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3779 = V_MAX_U16_dpp
19845 { 3783, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3783 = V_MAX_U32_dpp
19894 { 3832, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3832 = V_MIN_I16_dpp
19898 { 3836, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3836 = V_MIN_I32_dpp
19906 { 3844, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3844 = V_MIN_U16_dpp
19910 { 3848, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3848 = V_MIN_U32_dpp
19952 { 3890, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3890 = V_MUL_HI_I32_I24_dpp
19957 { 3895, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3895 = V_MUL_HI_U32_U24_dpp
19961 { 3899, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3899 = V_MUL_I32_I24_dpp
19970 { 3908, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3908 = V_MUL_LO_U16_dpp
19975 { 3913, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3913 = V_MUL_U32_U24_dpp
19987 { 3925, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3925 = V_OR_B32_dpp
20109 { 4047, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #4047 = V_SUBBREV_U32_dpp
20113 { 4051, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #4051 = V_SUBB_U32_dpp
20125 { 4063, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #4063 = V_SUBREV_I32_dpp
20129 { 4067, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4067 = V_SUBREV_U16_dpp
20133 { 4071, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4071 = V_SUBREV_U32_dpp
20146 { 4084, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #4084 = V_SUB_I32_dpp
20151 { 4089, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4089 = V_SUB_U16_dpp
20155 { 4093, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4093 = V_SUB_U32_dpp
20174 { 4112, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4112 = V_XNOR_B32_dpp
20179 { 4117, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4117 = V_XOR_B32_dpp
27964 { 11902, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #11902 = V_ADDC_CO_U32_dpp_gfx9
27968 { 11906, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #11906 = V_ADDC_U32_dpp_vi
27985 { 11923, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #11923 = V_ADD_CO_U32_dpp_gfx9
28029 { 11967, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #11967 = V_ADD_U16_dpp_vi
28034 { 11972, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #11972 = V_ADD_U32_dpp_gfx9
28035 { 11973, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #11973 = V_ADD_U32_dpp_vi
28050 { 11988, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #11988 = V_AND_B32_dpp_vi
28062 { 12000, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #12000 = V_ASHRREV_I16_dpp_vi
28070 { 12008, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #12008 = V_ASHRREV_I32_dpp_vi
30375 { 14313, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14313 = V_LSHLREV_B16_dpp_vi
30383 { 14321, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14321 = V_LSHLREV_B32_dpp_vi
30402 { 14340, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14340 = V_LSHRREV_B16_dpp_vi
30410 { 14348, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14348 = V_LSHRREV_B32_dpp_vi
30530 { 14468, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14468 = V_MAX_I16_dpp_vi
30538 { 14476, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14476 = V_MAX_I32_dpp_vi
30550 { 14488, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14488 = V_MAX_U16_dpp_vi
30558 { 14496, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14496 = V_MAX_U32_dpp_vi
30651 { 14589, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14589 = V_MIN_I16_dpp_vi
30659 { 14597, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14597 = V_MIN_I32_dpp_vi
30671 { 14609, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14609 = V_MIN_U16_dpp_vi
30679 { 14617, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14617 = V_MIN_U32_dpp_vi
30771 { 14709, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14709 = V_MUL_HI_I32_I24_dpp_vi
30786 { 14724, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14724 = V_MUL_HI_U32_U24_dpp_vi
30801 { 14739, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14739 = V_MUL_I32_I24_dpp_vi
30826 { 14764, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14764 = V_MUL_LO_U16_dpp_vi
30837 { 14775, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14775 = V_MUL_U32_U24_dpp_vi
30872 { 14810, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #14810 = V_OR_B32_dpp_vi
31122 { 15060, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #15060 = V_SUBBREV_CO_U32_dpp_gfx9
31126 { 15064, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #15064 = V_SUBBREV_U32_dpp_vi
31132 { 15070, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #15070 = V_SUBB_CO_U32_dpp_gfx9
31136 { 15074, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #15074 = V_SUBB_U32_dpp_vi
31153 { 15091, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #15091 = V_SUBREV_CO_U32_dpp_gfx9
31187 { 15125, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #15125 = V_SUBREV_U16_dpp_vi
31192 { 15130, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #15130 = V_SUBREV_U32_dpp_gfx9
31193 { 15131, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #15131 = V_SUBREV_U32_dpp_vi
31211 { 15149, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #15149 = V_SUB_CO_U32_dpp_gfx9
31250 { 15188, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #15188 = V_SUB_U16_dpp_vi
31255 { 15193, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #15193 = V_SUB_U32_dpp_gfx9
31256 { 15194, 8, 1, 8, 9, 0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #15194 = V_SUB_U32_dpp_vi
31304 { 15242, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #15242 = V_XNOR_B32_dpp_vi
31315 { 15253, 8, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #15253 = V_XOR_B32_dpp_vi