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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18381 { 2319, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2319 = V_ADD3_U32
18401 { 2339, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2339 = V_ADD_LSHL_U32
18410 { 2348, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2348 = V_ALIGNBIT_B32
18411 { 2349, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2349 = V_ALIGNBYTE_B32
18416 { 2354, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2354 = V_AND_OR_B32
18433 { 2371, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2371 = V_BFE_I32
18434 { 2372, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2372 = V_BFE_U32
18435 { 2373, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2373 = V_BFI_B32
19734 { 3672, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3672 = V_LERP_U8
19760 { 3698, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3698 = V_LSHL_ADD_U32
19766 { 3704, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3704 = V_LSHL_OR_B32
19817 { 3755, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3755 = V_MAX3_I32
19819 { 3757, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3757 = V_MAX3_U32
19856 { 3794, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3794 = V_MED3_I32
19858 { 3796, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3796 = V_MED3_U32
19882 { 3820, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3820 = V_MIN3_I32
19884 { 3822, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3822 = V_MIN3_U32
19986 { 3924, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3924 = V_OR3_B32
19994 { 3932, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3932 = V_PERM_B32
20173 { 4111, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #4111 = V_XAD_U32
20178 { 4116, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #4116 = V_XOR3_B32
27962 { 11900, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11900 = V_ADD3_U32_gfx10
27963 { 11901, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11901 = V_ADD3_U32_vi
28019 { 11957, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11957 = V_ADD_LSHL_U32_gfx10
28020 { 11958, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11958 = V_ADD_LSHL_U32_vi
28042 { 11980, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11980 = V_ALIGNBIT_B32_gfx10
28043 { 11981, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11981 = V_ALIGNBIT_B32_gfx6_gfx7
28044 { 11982, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11982 = V_ALIGNBIT_B32_vi
28045 { 11983, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11983 = V_ALIGNBYTE_B32_gfx10
28046 { 11984, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11984 = V_ALIGNBYTE_B32_gfx6_gfx7
28047 { 11985, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11985 = V_ALIGNBYTE_B32_vi
28060 { 11998, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11998 = V_AND_OR_B32_gfx10
28061 { 11999, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #11999 = V_AND_OR_B32_vi
28089 { 12027, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #12027 = V_BFE_I32_gfx10
28090 { 12028, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #12028 = V_BFE_I32_gfx6_gfx7
28091 { 12029, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #12029 = V_BFE_I32_vi
28092 { 12030, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #12030 = V_BFE_U32_gfx10
28093 { 12031, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #12031 = V_BFE_U32_gfx6_gfx7
28094 { 12032, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #12032 = V_BFE_U32_vi
28095 { 12033, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #12033 = V_BFI_B32_gfx10
28096 { 12034, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #12034 = V_BFI_B32_gfx6_gfx7
28097 { 12035, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #12035 = V_BFI_B32_vi
30341 { 14279, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14279 = V_LERP_U8_gfx10
30342 { 14280, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14280 = V_LERP_U8_gfx6_gfx7
30343 { 14281, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14281 = V_LERP_U8_vi
30395 { 14333, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14333 = V_LSHL_ADD_U32_gfx10
30396 { 14334, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14334 = V_LSHL_ADD_U32_vi
30400 { 14338, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14338 = V_LSHL_OR_B32_gfx10
30401 { 14339, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14339 = V_LSHL_OR_B32_vi
30497 { 14435, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14435 = V_MAX3_I32_gfx10
30498 { 14436, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14436 = V_MAX3_I32_gfx6_gfx7
30499 { 14437, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14437 = V_MAX3_I32_vi
30502 { 14440, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14440 = V_MAX3_U32_gfx10
30503 { 14441, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14441 = V_MAX3_U32_gfx6_gfx7
30504 { 14442, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14442 = V_MAX3_U32_vi
30583 { 14521, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14521 = V_MED3_I32_gfx10
30584 { 14522, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14522 = V_MED3_I32_gfx6_gfx7
30585 { 14523, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14523 = V_MED3_I32_vi
30588 { 14526, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14526 = V_MED3_U32_gfx10
30589 { 14527, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14527 = V_MED3_U32_gfx6_gfx7
30590 { 14528, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14528 = V_MED3_U32_vi
30618 { 14556, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14556 = V_MIN3_I32_gfx10
30619 { 14557, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14557 = V_MIN3_I32_gfx6_gfx7
30620 { 14558, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14558 = V_MIN3_I32_vi
30623 { 14561, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14561 = V_MIN3_U32_gfx10
30624 { 14562, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14562 = V_MIN3_U32_gfx6_gfx7
30625 { 14563, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14563 = V_MIN3_U32_vi
30868 { 14806, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14806 = V_OR3_B32_gfx10
30869 { 14807, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14807 = V_OR3_B32_vi
30886 { 14824, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14824 = V_PERM_B32_gfx10
30887 { 14825, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #14825 = V_PERM_B32_vi
31300 { 15238, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #15238 = V_XAD_U32_gfx10
31301 { 15239, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #15239 = V_XAD_U32_vi
31312 { 15250, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #15250 = V_XOR3_B32_gfx10