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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18199 { 2137, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2137 = TBUFFER_LOAD_FORMAT_D16_XY_ADDR64
18200 { 2138, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2138 = TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN
18201 { 2139, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2139 = TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_exact
18217 { 2155, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2155 = TBUFFER_LOAD_FORMAT_D16_X_ADDR64
18218 { 2156, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2156 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN
18219 { 2157, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2157 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_exact
18226 { 2164, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2164 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_ADDR64
18227 { 2165, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2165 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN
18228 { 2166, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2166 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_exact
18262 { 2200, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2200 = TBUFFER_LOAD_FORMAT_X_ADDR64
18263 { 2201, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2201 = TBUFFER_LOAD_FORMAT_X_BOTHEN
18264 { 2202, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2202 = TBUFFER_LOAD_FORMAT_X_BOTHEN_exact
18307 { 2245, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2245 = TBUFFER_STORE_FORMAT_D16_XY_ADDR64
18308 { 2246, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2246 = TBUFFER_STORE_FORMAT_D16_XY_BOTHEN
18309 { 2247, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2247 = TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact
18325 { 2263, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2263 = TBUFFER_STORE_FORMAT_D16_X_ADDR64
18326 { 2264, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2264 = TBUFFER_STORE_FORMAT_D16_X_BOTHEN
18327 { 2265, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2265 = TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact
18334 { 2272, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2272 = TBUFFER_STORE_FORMAT_D16_X_gfx80_ADDR64
18335 { 2273, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2273 = TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN
18336 { 2274, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2274 = TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact
18370 { 2308, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2308 = TBUFFER_STORE_FORMAT_X_ADDR64
18371 { 2309, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2309 = TBUFFER_STORE_FORMAT_X_BOTHEN
18372 { 2310, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2310 = TBUFFER_STORE_FORMAT_X_BOTHEN_exact
27784 { 11722, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11722 = TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10
27785 { 11723, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11723 = TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi
27796 { 11734, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11734 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10
27797 { 11735, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11735 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi
27804 { 11742, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11742 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80
27847 { 11785, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11785 = TBUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7
27848 { 11786, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11786 = TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx10
27849 { 11787, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11787 = TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7
27850 { 11788, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11788 = TBUFFER_LOAD_FORMAT_X_BOTHEN_vi
27884 { 11822, 11, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11822 = TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10
27885 { 11823, 11, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11823 = TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi
27896 { 11834, 11, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11834 = TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10
27897 { 11835, 11, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11835 = TBUFFER_STORE_FORMAT_D16_X_BOTHEN_vi
27904 { 11842, 11, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11842 = TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80
27947 { 11885, 11, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11885 = TBUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7
27948 { 11886, 11, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11886 = TBUFFER_STORE_FORMAT_X_BOTHEN_gfx10
27949 { 11887, 11, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11887 = TBUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7
27950 { 11888, 11, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #11888 = TBUFFER_STORE_FORMAT_X_BOTHEN_vi