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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18197 { 2135, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2135 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET
18198 { 2136, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2136 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_exact
18251 { 2189, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2189 = TBUFFER_LOAD_FORMAT_XYZ_OFFSET
18252 { 2190, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2190 = TBUFFER_LOAD_FORMAT_XYZ_OFFSET_exact
18305 { 2243, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2243 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET
18306 { 2244, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2244 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact
18359 { 2297, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2297 = TBUFFER_STORE_FORMAT_XYZ_OFFSET
18360 { 2298, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2298 = TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact
27783 { 11721, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #11721 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80
27831 { 11769, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #11769 = TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10
27832 { 11770, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #11770 = TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7
27833 { 11771, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #11771 = TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi
27883 { 11821, 10, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #11821 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80
27931 { 11869, 10, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #11869 = TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10
27932 { 11870, 10, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #11870 = TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7
27933 { 11871, 10, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #11871 = TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi