|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18179 { 2117, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2117 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET
18180 { 2118, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2118 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_exact
18242 { 2180, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2180 = TBUFFER_LOAD_FORMAT_XYZW_OFFSET
18243 { 2181, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2181 = TBUFFER_LOAD_FORMAT_XYZW_OFFSET_exact
18287 { 2225, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2225 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET
18288 { 2226, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2226 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact
18350 { 2288, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2288 = TBUFFER_STORE_FORMAT_XYZW_OFFSET
18351 { 2289, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2289 = TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact
27771 { 11709, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #11709 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80
27818 { 11756, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #11756 = TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10
27819 { 11757, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #11757 = TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7
27820 { 11758, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #11758 = TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi
27871 { 11809, 10, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000300020000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #11809 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80
27918 { 11856, 10, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #11856 = TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10
27919 { 11857, 10, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #11857 = TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7
27920 { 11858, 10, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300020000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #11858 = TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi