|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17733 { 1671, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1671 = S_ABSDIFF_I32
17735 { 1673, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, ImplicitList1, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1673 = S_ADDC_U32
17737 { 1675, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1675 = S_ADD_I32
17738 { 1676, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1676 = S_ADD_U32
17745 { 1683, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1683 = S_ANDN2_B32
17746 { 1684, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1684 = S_ANDN2_B32_term
17753 { 1691, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1691 = S_AND_B32
17757 { 1695, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1695 = S_ASHR_I32
17871 { 1809, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1809 = S_BFE_I32
17873 { 1811, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1811 = S_BFE_U32
17875 { 1813, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1813 = S_BFM_B32
18023 { 1961, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, ImplicitList1, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1961 = S_CSELECT_B32
18055 { 1993, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1993 = S_LSHL1_ADD_U32
18056 { 1994, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1994 = S_LSHL2_ADD_U32
18057 { 1995, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1995 = S_LSHL3_ADD_U32
18058 { 1996, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1996 = S_LSHL4_ADD_U32
18059 { 1997, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1997 = S_LSHL_B32
18061 { 1999, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1999 = S_LSHR_B32
18063 { 2001, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2001 = S_MAX_I32
18064 { 2002, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2002 = S_MAX_U32
18067 { 2005, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2005 = S_MIN_I32
18068 { 2006, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2006 = S_MIN_U32
18082 { 2020, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2020 = S_MUL_HI_I32
18083 { 2021, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2021 = S_MUL_HI_U32
18084 { 2022, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2022 = S_MUL_I32
18085 { 2023, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2023 = S_NAND_B32
18089 { 2027, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2027 = S_NOR_B32
18097 { 2035, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2035 = S_ORN2_B32
18101 { 2039, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2039 = S_OR_B32
18102 { 2040, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2040 = S_OR_B32_term
18106 { 2044, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2044 = S_PACK_HH_B32_B16
18107 { 2045, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2045 = S_PACK_LH_B32_B16
18108 { 2046, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2046 = S_PACK_LL_B32_B16
18138 { 2076, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, ImplicitList1, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2076 = S_SUBB_U32
18141 { 2079, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2079 = S_SUB_I32
18142 { 2080, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2080 = S_SUB_U32
18153 { 2091, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2091 = S_XNOR_B32
18157 { 2095, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2095 = S_XOR_B32
18158 { 2096, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2096 = S_XOR_B32_term
26738 { 10676, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10676 = S_ABSDIFF_I32_gfx10
26739 { 10677, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10677 = S_ABSDIFF_I32_gfx6_gfx7
26740 { 10678, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10678 = S_ABSDIFF_I32_vi
26744 { 10682, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10682 = S_ADDC_U32_gfx10
26745 { 10683, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10683 = S_ADDC_U32_gfx6_gfx7
26746 { 10684, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10684 = S_ADDC_U32_vi
26750 { 10688, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10688 = S_ADD_I32_gfx10
26751 { 10689, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10689 = S_ADD_I32_gfx6_gfx7
26752 { 10690, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10690 = S_ADD_I32_vi
26753 { 10691, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10691 = S_ADD_U32_gfx10
26754 { 10692, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10692 = S_ADD_U32_gfx6_gfx7
26755 { 10693, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10693 = S_ADD_U32_vi
26762 { 10700, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10700 = S_ANDN2_B32_gfx10
26763 { 10701, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10701 = S_ANDN2_B32_gfx6_gfx7
26764 { 10702, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10702 = S_ANDN2_B32_vi
26775 { 10713, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10713 = S_AND_B32_gfx10
26776 { 10714, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10714 = S_AND_B32_gfx6_gfx7
26777 { 10715, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10715 = S_AND_B32_vi
26785 { 10723, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10723 = S_ASHR_I32_gfx10
26786 { 10724, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10724 = S_ASHR_I32_gfx6_gfx7
26787 { 10725, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10725 = S_ASHR_I32_vi
27020 { 10958, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10958 = S_BFE_I32_gfx10
27021 { 10959, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10959 = S_BFE_I32_gfx6_gfx7
27022 { 10960, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10960 = S_BFE_I32_vi
27026 { 10964, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10964 = S_BFE_U32_gfx10
27027 { 10965, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10965 = S_BFE_U32_gfx6_gfx7
27028 { 10966, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10966 = S_BFE_U32_vi
27032 { 10970, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10970 = S_BFM_B32_gfx10
27033 { 10971, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10971 = S_BFM_B32_gfx6_gfx7
27034 { 10972, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #10972 = S_BFM_B32_vi
27408 { 11346, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11346 = S_CSELECT_B32_gfx10
27409 { 11347, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11347 = S_CSELECT_B32_gfx6_gfx7
27410 { 11348, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11348 = S_CSELECT_B32_vi
27505 { 11443, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11443 = S_LSHL1_ADD_U32_gfx10
27506 { 11444, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11444 = S_LSHL1_ADD_U32_vi
27507 { 11445, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11445 = S_LSHL2_ADD_U32_gfx10
27508 { 11446, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11446 = S_LSHL2_ADD_U32_vi
27509 { 11447, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11447 = S_LSHL3_ADD_U32_gfx10
27510 { 11448, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11448 = S_LSHL3_ADD_U32_vi
27511 { 11449, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11449 = S_LSHL4_ADD_U32_gfx10
27512 { 11450, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11450 = S_LSHL4_ADD_U32_vi
27513 { 11451, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11451 = S_LSHL_B32_gfx10
27514 { 11452, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11452 = S_LSHL_B32_gfx6_gfx7
27515 { 11453, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11453 = S_LSHL_B32_vi
27519 { 11457, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11457 = S_LSHR_B32_gfx10
27520 { 11458, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11458 = S_LSHR_B32_gfx6_gfx7
27521 { 11459, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11459 = S_LSHR_B32_vi
27525 { 11463, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11463 = S_MAX_I32_gfx10
27526 { 11464, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11464 = S_MAX_I32_gfx6_gfx7
27527 { 11465, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11465 = S_MAX_I32_vi
27528 { 11466, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11466 = S_MAX_U32_gfx10
27529 { 11467, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11467 = S_MAX_U32_gfx6_gfx7
27530 { 11468, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11468 = S_MAX_U32_vi
27536 { 11474, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11474 = S_MIN_I32_gfx10
27537 { 11475, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11475 = S_MIN_I32_gfx6_gfx7
27538 { 11476, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11476 = S_MIN_I32_vi
27539 { 11477, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11477 = S_MIN_U32_gfx10
27540 { 11478, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11478 = S_MIN_U32_gfx6_gfx7
27541 { 11479, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11479 = S_MIN_U32_vi
27572 { 11510, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11510 = S_MUL_HI_I32_gfx10
27573 { 11511, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11511 = S_MUL_HI_I32_vi
27574 { 11512, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11512 = S_MUL_HI_U32_gfx10
27575 { 11513, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11513 = S_MUL_HI_U32_vi
27576 { 11514, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11514 = S_MUL_I32_gfx10
27577 { 11515, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11515 = S_MUL_I32_gfx6_gfx7
27578 { 11516, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11516 = S_MUL_I32_vi
27579 { 11517, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11517 = S_NAND_B32_gfx10
27580 { 11518, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11518 = S_NAND_B32_gfx6_gfx7
27581 { 11519, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11519 = S_NAND_B32_vi
27590 { 11528, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11528 = S_NOR_B32_gfx10
27591 { 11529, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11529 = S_NOR_B32_gfx6_gfx7
27592 { 11530, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11530 = S_NOR_B32_vi
27609 { 11547, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11547 = S_ORN2_B32_gfx10
27610 { 11548, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11548 = S_ORN2_B32_gfx6_gfx7
27611 { 11549, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11549 = S_ORN2_B32_vi
27619 { 11557, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11557 = S_OR_B32_gfx10
27620 { 11558, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11558 = S_OR_B32_gfx6_gfx7
27621 { 11559, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11559 = S_OR_B32_vi
27629 { 11567, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11567 = S_PACK_HH_B32_B16_gfx10
27630 { 11568, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11568 = S_PACK_HH_B32_B16_vi
27631 { 11569, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11569 = S_PACK_LH_B32_B16_gfx10
27632 { 11570, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11570 = S_PACK_LH_B32_B16_vi
27633 { 11571, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11571 = S_PACK_LL_B32_B16_gfx10
27634 { 11572, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11572 = S_PACK_LL_B32_B16_vi
27708 { 11646, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11646 = S_SUBB_U32_gfx10
27709 { 11647, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11647 = S_SUBB_U32_gfx6_gfx7
27710 { 11648, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11648 = S_SUBB_U32_vi
27713 { 11651, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11651 = S_SUB_I32_gfx10
27714 { 11652, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11652 = S_SUB_I32_gfx6_gfx7
27715 { 11653, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11653 = S_SUB_I32_vi
27716 { 11654, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11654 = S_SUB_U32_gfx10
27717 { 11655, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11655 = S_SUB_U32_gfx6_gfx7
27718 { 11656, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11656 = S_SUB_U32_vi
27740 { 11678, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11678 = S_XNOR_B32_gfx10
27741 { 11679, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11679 = S_XNOR_B32_gfx6_gfx7
27742 { 11680, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11680 = S_XNOR_B32_vi
27750 { 11688, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11688 = S_XOR_B32_gfx10
27751 { 11689, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11689 = S_XOR_B32_gfx6_gfx7
27752 { 11690, 3, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #11690 = S_XOR_B32_vi