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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17707 { 1645, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1645 = SI_SPILL_S32_RESTORE
17708 { 1646, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1646 = SI_SPILL_S32_SAVE
18008 { 1946, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x21ULL, ImplicitList1, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1946 = S_CMOVK_I32
18011 { 1949, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1949 = S_CMPK_EQ_I32
18012 { 1950, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1950 = S_CMPK_EQ_U32
18013 { 1951, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1951 = S_CMPK_GE_I32
18014 { 1952, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1952 = S_CMPK_GE_U32
18015 { 1953, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1953 = S_CMPK_GT_I32
18016 { 1954, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1954 = S_CMPK_GT_U32
18017 { 1955, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1955 = S_CMPK_LE_I32
18018 { 1956, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1956 = S_CMPK_LE_U32
18019 { 1957, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1957 = S_CMPK_LG_I32
18020 { 1958, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1958 = S_CMPK_LG_U32
18021 { 1959, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1959 = S_CMPK_LT_I32
18022 { 1960, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1960 = S_CMPK_LT_U32
18042 { 1980, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1980 = S_GETREG_B32
18069 { 2007, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2007 = S_MOVK_I32
18127 { 2065, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2065 = S_SETREG_B32
18147 { 2085, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2085 = S_WAITCNT_EXPCNT
18148 { 2086, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2086 = S_WAITCNT_LGKMCNT
18149 { 2087, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2087 = S_WAITCNT_VMCNT
18150 { 2088, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2088 = S_WAITCNT_VSCNT
27348 { 11286, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11286 = S_CMOVK_I32_gfx10
27349 { 11287, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11287 = S_CMOVK_I32_gfx6_gfx7
27350 { 11288, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11288 = S_CMOVK_I32_vi
27357 { 11295, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11295 = S_CMPK_EQ_I32_gfx10
27358 { 11296, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11296 = S_CMPK_EQ_I32_gfx6_gfx7
27359 { 11297, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11297 = S_CMPK_EQ_I32_vi
27360 { 11298, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11298 = S_CMPK_EQ_U32_gfx10
27361 { 11299, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11299 = S_CMPK_EQ_U32_gfx6_gfx7
27362 { 11300, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11300 = S_CMPK_EQ_U32_vi
27363 { 11301, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11301 = S_CMPK_GE_I32_gfx10
27364 { 11302, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11302 = S_CMPK_GE_I32_gfx6_gfx7
27365 { 11303, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11303 = S_CMPK_GE_I32_vi
27366 { 11304, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11304 = S_CMPK_GE_U32_gfx10
27367 { 11305, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11305 = S_CMPK_GE_U32_gfx6_gfx7
27368 { 11306, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11306 = S_CMPK_GE_U32_vi
27369 { 11307, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11307 = S_CMPK_GT_I32_gfx10
27370 { 11308, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11308 = S_CMPK_GT_I32_gfx6_gfx7
27371 { 11309, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11309 = S_CMPK_GT_I32_vi
27372 { 11310, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11310 = S_CMPK_GT_U32_gfx10
27373 { 11311, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11311 = S_CMPK_GT_U32_gfx6_gfx7
27374 { 11312, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11312 = S_CMPK_GT_U32_vi
27375 { 11313, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11313 = S_CMPK_LE_I32_gfx10
27376 { 11314, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11314 = S_CMPK_LE_I32_gfx6_gfx7
27377 { 11315, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11315 = S_CMPK_LE_I32_vi
27378 { 11316, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11316 = S_CMPK_LE_U32_gfx10
27379 { 11317, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11317 = S_CMPK_LE_U32_gfx6_gfx7
27380 { 11318, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11318 = S_CMPK_LE_U32_vi
27381 { 11319, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11319 = S_CMPK_LG_I32_gfx10
27382 { 11320, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11320 = S_CMPK_LG_I32_gfx6_gfx7
27383 { 11321, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11321 = S_CMPK_LG_I32_vi
27384 { 11322, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11322 = S_CMPK_LG_U32_gfx10
27385 { 11323, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11323 = S_CMPK_LG_U32_gfx6_gfx7
27386 { 11324, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11324 = S_CMPK_LG_U32_vi
27387 { 11325, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11325 = S_CMPK_LT_I32_gfx10
27388 { 11326, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11326 = S_CMPK_LT_I32_gfx6_gfx7
27389 { 11327, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11327 = S_CMPK_LT_I32_vi
27390 { 11328, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11328 = S_CMPK_LT_U32_gfx10
27391 { 11329, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11329 = S_CMPK_LT_U32_gfx6_gfx7
27392 { 11330, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11330 = S_CMPK_LT_U32_vi
27462 { 11400, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11400 = S_GETREG_B32_gfx10
27463 { 11401, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11401 = S_GETREG_B32_gfx6_gfx7
27464 { 11402, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11402 = S_GETREG_B32_vi
27542 { 11480, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11480 = S_MOVK_I32_gfx10
27543 { 11481, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11481 = S_MOVK_I32_gfx6_gfx7
27544 { 11482, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11482 = S_MOVK_I32_vi
27678 { 11616, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11616 = S_SETREG_B32_gfx10
27679 { 11617, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11617 = S_SETREG_B32_gfx6_gfx7
27680 { 11618, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11618 = S_SETREG_B32_vi
27728 { 11666, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11666 = S_WAITCNT_EXPCNT_gfx10
27730 { 11668, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11668 = S_WAITCNT_LGKMCNT_gfx10
27731 { 11669, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11669 = S_WAITCNT_VMCNT_gfx10
27732 { 11670, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #11670 = S_WAITCNT_VSCNT_gfx10