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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17655 { 1593, 1, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #1593 = SI_BR_UNDEF
27056 { 10994, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #10994 = S_BRANCH
27057 { 10995, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #10995 = S_BRANCH_pad_s_nop
27321 { 11259, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11259 = S_CBRANCH_CDBGSYS
27322 { 11260, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11260 = S_CBRANCH_CDBGSYS_AND_USER
27323 { 11261, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11261 = S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop
27324 { 11262, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11262 = S_CBRANCH_CDBGSYS_OR_USER
27325 { 11263, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11263 = S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop
27326 { 11264, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11264 = S_CBRANCH_CDBGSYS_pad_s_nop
27327 { 11265, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11265 = S_CBRANCH_CDBGUSER
27328 { 11266, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11266 = S_CBRANCH_CDBGUSER_pad_s_nop
27329 { 11267, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList2, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11267 = S_CBRANCH_EXECNZ
27330 { 11268, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList2, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11268 = S_CBRANCH_EXECNZ_pad_s_nop
27331 { 11269, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList2, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11269 = S_CBRANCH_EXECZ
27332 { 11270, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList2, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11270 = S_CBRANCH_EXECZ_pad_s_nop
27339 { 11277, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11277 = S_CBRANCH_SCC0
27340 { 11278, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11278 = S_CBRANCH_SCC0_pad_s_nop
27341 { 11279, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11279 = S_CBRANCH_SCC1
27342 { 11280, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11280 = S_CBRANCH_SCC1_pad_s_nop
27343 { 11281, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11281 = S_CBRANCH_VCCNZ
27344 { 11282, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11282 = S_CBRANCH_VCCNZ_pad_s_nop
27345 { 11283, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11283 = S_CBRANCH_VCCZ
27346 { 11284, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11284 = S_CBRANCH_VCCZ_pad_s_nop