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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17441 { 1379, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1379 = GLOBAL_ATOMIC_ADD_X2_SADDR
17449 { 1387, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1387 = GLOBAL_ATOMIC_AND_X2_SADDR
17453 { 1391, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1391 = GLOBAL_ATOMIC_CMPSWAP_SADDR
17465 { 1403, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1403 = GLOBAL_ATOMIC_DEC_X2_SADDR
17473 { 1411, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1411 = GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR
17481 { 1419, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1419 = GLOBAL_ATOMIC_FMAX_X2_SADDR
17489 { 1427, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1427 = GLOBAL_ATOMIC_FMIN_X2_SADDR
17497 { 1435, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1435 = GLOBAL_ATOMIC_INC_X2_SADDR
17505 { 1443, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1443 = GLOBAL_ATOMIC_OR_X2_SADDR
17515 { 1453, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1453 = GLOBAL_ATOMIC_SMAX_X2_SADDR
17523 { 1461, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1461 = GLOBAL_ATOMIC_SMIN_X2_SADDR
17531 { 1469, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1469 = GLOBAL_ATOMIC_SUB_X2_SADDR
17539 { 1477, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1477 = GLOBAL_ATOMIC_SWAP_X2_SADDR
17547 { 1485, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1485 = GLOBAL_ATOMIC_UMAX_X2_SADDR
17555 { 1493, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1493 = GLOBAL_ATOMIC_UMIN_X2_SADDR
17563 { 1501, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1501 = GLOBAL_ATOMIC_XOR_X2_SADDR
22233 { 6171, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6171 = GLOBAL_ATOMIC_ADD_X2_SADDR_gfx10
22234 { 6172, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6172 = GLOBAL_ATOMIC_ADD_X2_SADDR_vi
22249 { 6187, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6187 = GLOBAL_ATOMIC_AND_X2_SADDR_gfx10
22250 { 6188, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6188 = GLOBAL_ATOMIC_AND_X2_SADDR_vi
22259 { 6197, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6197 = GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx10
22260 { 6198, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6198 = GLOBAL_ATOMIC_CMPSWAP_SADDR_vi
22281 { 6219, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6219 = GLOBAL_ATOMIC_DEC_X2_SADDR_gfx10
22282 { 6220, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6220 = GLOBAL_ATOMIC_DEC_X2_SADDR_vi
22292 { 6230, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6230 = GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_gfx10
22300 { 6238, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6238 = GLOBAL_ATOMIC_FMAX_X2_SADDR_gfx10
22308 { 6246, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6246 = GLOBAL_ATOMIC_FMIN_X2_SADDR_gfx10
22321 { 6259, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6259 = GLOBAL_ATOMIC_INC_X2_SADDR_gfx10
22322 { 6260, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6260 = GLOBAL_ATOMIC_INC_X2_SADDR_vi
22337 { 6275, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6275 = GLOBAL_ATOMIC_OR_X2_SADDR_gfx10
22338 { 6276, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6276 = GLOBAL_ATOMIC_OR_X2_SADDR_vi
22355 { 6293, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6293 = GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx10
22356 { 6294, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6294 = GLOBAL_ATOMIC_SMAX_X2_SADDR_vi
22371 { 6309, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6309 = GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx10
22372 { 6310, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6310 = GLOBAL_ATOMIC_SMIN_X2_SADDR_vi
22387 { 6325, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6325 = GLOBAL_ATOMIC_SUB_X2_SADDR_gfx10
22388 { 6326, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6326 = GLOBAL_ATOMIC_SUB_X2_SADDR_vi
22403 { 6341, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6341 = GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx10
22404 { 6342, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6342 = GLOBAL_ATOMIC_SWAP_X2_SADDR_vi
22419 { 6357, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6357 = GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx10
22420 { 6358, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6358 = GLOBAL_ATOMIC_UMAX_X2_SADDR_vi
22435 { 6373, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6373 = GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx10
22436 { 6374, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6374 = GLOBAL_ATOMIC_UMIN_X2_SADDR_vi
22451 { 6389, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6389 = GLOBAL_ATOMIC_XOR_X2_SADDR_gfx10
22452 { 6390, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8080100200000ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #6390 = GLOBAL_ATOMIC_XOR_X2_SADDR_vi