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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17658 { 1596, 4, 1, 12, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo146, -1 ,nullptr }, // Inst #1596 = SI_ELSE
17659 { 1597, 1, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo147, -1 ,nullptr }, // Inst #1597 = SI_END_CF
17660 { 1598, 3, 1, 12, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo148, -1 ,nullptr }, // Inst #1598 = SI_IF
17681 { 1619, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo164, -1 ,nullptr }, // Inst #1619 = SI_LOOP
17741 { 1679, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #1679 = S_ANDN1_SAVEEXEC_B32
17742 { 1680, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #1680 = S_ANDN1_SAVEEXEC_B64
17743 { 1681, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #1681 = S_ANDN1_WREXEC_B32
17744 { 1682, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #1682 = S_ANDN1_WREXEC_B64
17749 { 1687, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #1687 = S_ANDN2_SAVEEXEC_B32
17750 { 1688, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #1688 = S_ANDN2_SAVEEXEC_B64
17751 { 1689, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #1689 = S_ANDN2_WREXEC_B32
17752 { 1690, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #1690 = S_ANDN2_WREXEC_B64
17755 { 1693, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #1693 = S_AND_SAVEEXEC_B32
17756 { 1694, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #1694 = S_AND_SAVEEXEC_B64
18087 { 2025, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2025 = S_NAND_SAVEEXEC_B32
18088 { 2026, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2026 = S_NAND_SAVEEXEC_B64
18091 { 2029, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2029 = S_NOR_SAVEEXEC_B32
18092 { 2030, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2030 = S_NOR_SAVEEXEC_B64
18095 { 2033, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2033 = S_ORN1_SAVEEXEC_B32
18096 { 2034, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2034 = S_ORN1_SAVEEXEC_B64
18099 { 2037, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2037 = S_ORN2_SAVEEXEC_B32
18100 { 2038, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2038 = S_ORN2_SAVEEXEC_B64
18104 { 2042, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2042 = S_OR_SAVEEXEC_B32
18105 { 2043, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2043 = S_OR_SAVEEXEC_B64
18155 { 2093, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2093 = S_XNOR_SAVEEXEC_B32
18156 { 2094, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2094 = S_XNOR_SAVEEXEC_B64
18161 { 2099, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2099 = S_XOR_SAVEEXEC_B32
18162 { 2100, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2100 = S_XOR_SAVEEXEC_B64