|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17346 { 1284, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1284 = FLAT_ATOMIC_ADD
17347 { 1285, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1285 = FLAT_ATOMIC_ADD_RTN
17348 { 1286, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1286 = FLAT_ATOMIC_ADD_X2
17349 { 1287, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1287 = FLAT_ATOMIC_ADD_X2_RTN
17350 { 1288, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1288 = FLAT_ATOMIC_AND
17351 { 1289, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1289 = FLAT_ATOMIC_AND_RTN
17352 { 1290, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1290 = FLAT_ATOMIC_AND_X2
17353 { 1291, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1291 = FLAT_ATOMIC_AND_X2_RTN
17354 { 1292, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1292 = FLAT_ATOMIC_CMPSWAP
17355 { 1293, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1293 = FLAT_ATOMIC_CMPSWAP_RTN
17356 { 1294, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1294 = FLAT_ATOMIC_CMPSWAP_X2
17357 { 1295, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1295 = FLAT_ATOMIC_CMPSWAP_X2_RTN
17358 { 1296, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1296 = FLAT_ATOMIC_DEC
17359 { 1297, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1297 = FLAT_ATOMIC_DEC_RTN
17360 { 1298, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1298 = FLAT_ATOMIC_DEC_X2
17361 { 1299, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1299 = FLAT_ATOMIC_DEC_X2_RTN
17362 { 1300, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1300 = FLAT_ATOMIC_FCMPSWAP
17363 { 1301, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1301 = FLAT_ATOMIC_FCMPSWAP_RTN
17364 { 1302, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1302 = FLAT_ATOMIC_FCMPSWAP_X2
17365 { 1303, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1303 = FLAT_ATOMIC_FCMPSWAP_X2_RTN
17366 { 1304, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1304 = FLAT_ATOMIC_FMAX
17367 { 1305, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1305 = FLAT_ATOMIC_FMAX_RTN
17368 { 1306, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1306 = FLAT_ATOMIC_FMAX_X2
17369 { 1307, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1307 = FLAT_ATOMIC_FMAX_X2_RTN
17370 { 1308, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1308 = FLAT_ATOMIC_FMIN
17371 { 1309, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1309 = FLAT_ATOMIC_FMIN_RTN
17372 { 1310, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1310 = FLAT_ATOMIC_FMIN_X2
17373 { 1311, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1311 = FLAT_ATOMIC_FMIN_X2_RTN
17374 { 1312, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1312 = FLAT_ATOMIC_INC
17375 { 1313, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1313 = FLAT_ATOMIC_INC_RTN
17376 { 1314, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1314 = FLAT_ATOMIC_INC_X2
17377 { 1315, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1315 = FLAT_ATOMIC_INC_X2_RTN
17378 { 1316, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1316 = FLAT_ATOMIC_OR
17379 { 1317, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1317 = FLAT_ATOMIC_OR_RTN
17380 { 1318, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1318 = FLAT_ATOMIC_OR_X2
17381 { 1319, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1319 = FLAT_ATOMIC_OR_X2_RTN
17382 { 1320, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1320 = FLAT_ATOMIC_SMAX
17383 { 1321, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1321 = FLAT_ATOMIC_SMAX_RTN
17384 { 1322, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1322 = FLAT_ATOMIC_SMAX_X2
17385 { 1323, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1323 = FLAT_ATOMIC_SMAX_X2_RTN
17386 { 1324, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1324 = FLAT_ATOMIC_SMIN
17387 { 1325, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1325 = FLAT_ATOMIC_SMIN_RTN
17388 { 1326, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1326 = FLAT_ATOMIC_SMIN_X2
17389 { 1327, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1327 = FLAT_ATOMIC_SMIN_X2_RTN
17390 { 1328, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1328 = FLAT_ATOMIC_SUB
17391 { 1329, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1329 = FLAT_ATOMIC_SUB_RTN
17392 { 1330, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1330 = FLAT_ATOMIC_SUB_X2
17393 { 1331, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1331 = FLAT_ATOMIC_SUB_X2_RTN
17394 { 1332, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1332 = FLAT_ATOMIC_SWAP
17395 { 1333, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1333 = FLAT_ATOMIC_SWAP_RTN
17396 { 1334, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1334 = FLAT_ATOMIC_SWAP_X2
17397 { 1335, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1335 = FLAT_ATOMIC_SWAP_X2_RTN
17398 { 1336, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1336 = FLAT_ATOMIC_UMAX
17399 { 1337, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1337 = FLAT_ATOMIC_UMAX_RTN
17400 { 1338, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1338 = FLAT_ATOMIC_UMAX_X2
17401 { 1339, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1339 = FLAT_ATOMIC_UMAX_X2_RTN
17402 { 1340, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1340 = FLAT_ATOMIC_UMIN
17403 { 1341, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1341 = FLAT_ATOMIC_UMIN_RTN
17404 { 1342, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1342 = FLAT_ATOMIC_UMIN_X2
17405 { 1343, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1343 = FLAT_ATOMIC_UMIN_X2_RTN
17406 { 1344, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1344 = FLAT_ATOMIC_XOR
17407 { 1345, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1345 = FLAT_ATOMIC_XOR_RTN
17408 { 1346, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1346 = FLAT_ATOMIC_XOR_X2
17409 { 1347, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1347 = FLAT_ATOMIC_XOR_X2_RTN
17410 { 1348, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1348 = FLAT_LOAD_DWORD
17411 { 1349, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1349 = FLAT_LOAD_DWORDX2
17412 { 1350, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #1350 = FLAT_LOAD_DWORDX3
17413 { 1351, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1351 = FLAT_LOAD_DWORDX4
17414 { 1352, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1352 = FLAT_LOAD_SBYTE
17415 { 1353, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1353 = FLAT_LOAD_SBYTE_D16
17416 { 1354, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1354 = FLAT_LOAD_SBYTE_D16_HI
17417 { 1355, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1355 = FLAT_LOAD_SHORT_D16
17418 { 1356, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1356 = FLAT_LOAD_SHORT_D16_HI
17419 { 1357, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1357 = FLAT_LOAD_SSHORT
17420 { 1358, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1358 = FLAT_LOAD_UBYTE
17421 { 1359, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1359 = FLAT_LOAD_UBYTE_D16
17422 { 1360, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1360 = FLAT_LOAD_UBYTE_D16_HI
17423 { 1361, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1361 = FLAT_LOAD_USHORT
17424 { 1362, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1362 = FLAT_STORE_BYTE
17425 { 1363, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1363 = FLAT_STORE_BYTE_D16_HI
17426 { 1364, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1364 = FLAT_STORE_DWORD
17427 { 1365, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1365 = FLAT_STORE_DWORDX2
17428 { 1366, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #1366 = FLAT_STORE_DWORDX3
17429 { 1367, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #1367 = FLAT_STORE_DWORDX4
17430 { 1368, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1368 = FLAT_STORE_SHORT
17431 { 1369, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1369 = FLAT_STORE_SHORT_D16_HI
17611 { 1549, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1549 = SCRATCH_LOAD_DWORD
17612 { 1550, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1550 = SCRATCH_LOAD_DWORDX2
17613 { 1551, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1551 = SCRATCH_LOAD_DWORDX2_SADDR
17614 { 1552, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1552 = SCRATCH_LOAD_DWORDX3
17615 { 1553, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1553 = SCRATCH_LOAD_DWORDX3_SADDR
17616 { 1554, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1554 = SCRATCH_LOAD_DWORDX4
17617 { 1555, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1555 = SCRATCH_LOAD_DWORDX4_SADDR
17618 { 1556, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1556 = SCRATCH_LOAD_DWORD_SADDR
17619 { 1557, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1557 = SCRATCH_LOAD_SBYTE
17620 { 1558, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1558 = SCRATCH_LOAD_SBYTE_D16
17621 { 1559, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1559 = SCRATCH_LOAD_SBYTE_D16_HI
17622 { 1560, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1560 = SCRATCH_LOAD_SBYTE_D16_HI_SADDR
17623 { 1561, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1561 = SCRATCH_LOAD_SBYTE_D16_SADDR
17624 { 1562, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1562 = SCRATCH_LOAD_SBYTE_SADDR
17625 { 1563, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1563 = SCRATCH_LOAD_SHORT_D16
17626 { 1564, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1564 = SCRATCH_LOAD_SHORT_D16_HI
17627 { 1565, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1565 = SCRATCH_LOAD_SHORT_D16_HI_SADDR
17628 { 1566, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1566 = SCRATCH_LOAD_SHORT_D16_SADDR
17629 { 1567, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1567 = SCRATCH_LOAD_SSHORT
17630 { 1568, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1568 = SCRATCH_LOAD_SSHORT_SADDR
17631 { 1569, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1569 = SCRATCH_LOAD_UBYTE
17632 { 1570, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1570 = SCRATCH_LOAD_UBYTE_D16
17633 { 1571, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1571 = SCRATCH_LOAD_UBYTE_D16_HI
17634 { 1572, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1572 = SCRATCH_LOAD_UBYTE_D16_HI_SADDR
17635 { 1573, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1573 = SCRATCH_LOAD_UBYTE_D16_SADDR
17636 { 1574, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1574 = SCRATCH_LOAD_UBYTE_SADDR
17637 { 1575, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1575 = SCRATCH_LOAD_USHORT
17638 { 1576, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1576 = SCRATCH_LOAD_USHORT_SADDR
17639 { 1577, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1577 = SCRATCH_STORE_BYTE
17640 { 1578, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1578 = SCRATCH_STORE_BYTE_D16_HI
17641 { 1579, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1579 = SCRATCH_STORE_BYTE_D16_HI_SADDR
17642 { 1580, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1580 = SCRATCH_STORE_BYTE_SADDR
17643 { 1581, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1581 = SCRATCH_STORE_DWORD
17644 { 1582, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1582 = SCRATCH_STORE_DWORDX2
17645 { 1583, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1583 = SCRATCH_STORE_DWORDX2_SADDR
17646 { 1584, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1584 = SCRATCH_STORE_DWORDX3
17647 { 1585, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1585 = SCRATCH_STORE_DWORDX3_SADDR
17648 { 1586, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1586 = SCRATCH_STORE_DWORDX4
17649 { 1587, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1587 = SCRATCH_STORE_DWORDX4_SADDR
17650 { 1588, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1588 = SCRATCH_STORE_DWORD_SADDR
17651 { 1589, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1589 = SCRATCH_STORE_SHORT
17652 { 1590, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1590 = SCRATCH_STORE_SHORT_D16_HI
17653 { 1591, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1591 = SCRATCH_STORE_SHORT_D16_HI_SADDR
17654 { 1592, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1592 = SCRATCH_STORE_SHORT_SADDR