|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17088 { 1026, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1026 = DS_ADD_F32
17090 { 1028, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1028 = DS_ADD_RTN_F32
17092 { 1030, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1030 = DS_ADD_RTN_U32
17094 { 1032, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1032 = DS_ADD_RTN_U64
17096 { 1034, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1034 = DS_ADD_SRC2_F32
17097 { 1035, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1035 = DS_ADD_SRC2_U32
17098 { 1036, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1036 = DS_ADD_SRC2_U64
17099 { 1037, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1037 = DS_ADD_U32
17101 { 1039, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1039 = DS_ADD_U64
17103 { 1041, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1041 = DS_AND_B32
17105 { 1043, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1043 = DS_AND_B64
17107 { 1045, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1045 = DS_AND_RTN_B32
17109 { 1047, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1047 = DS_AND_RTN_B64
17111 { 1049, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1049 = DS_AND_SRC2_B32
17112 { 1050, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1050 = DS_AND_SRC2_B64
17113 { 1051, 3, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1051 = DS_APPEND
17115 { 1053, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1053 = DS_CMPST_B32
17117 { 1055, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1055 = DS_CMPST_B64
17119 { 1057, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1057 = DS_CMPST_F32
17121 { 1059, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1059 = DS_CMPST_F64
17123 { 1061, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1061 = DS_CMPST_RTN_B32
17125 { 1063, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #1063 = DS_CMPST_RTN_B64
17127 { 1065, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1065 = DS_CMPST_RTN_F32
17129 { 1067, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #1067 = DS_CMPST_RTN_F64
17131 { 1069, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1069 = DS_CONDXCHG32_RTN_B64
17133 { 1071, 3, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1071 = DS_CONSUME
17134 { 1072, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1072 = DS_DEC_RTN_U32
17136 { 1074, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1074 = DS_DEC_RTN_U64
17138 { 1076, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1076 = DS_DEC_SRC2_U32
17139 { 1077, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1077 = DS_DEC_SRC2_U64
17140 { 1078, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1078 = DS_DEC_U32
17142 { 1080, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1080 = DS_DEC_U64
17144 { 1082, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1082 = DS_GWS_BARRIER
17145 { 1083, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1083 = DS_GWS_INIT
17146 { 1084, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1084 = DS_GWS_SEMA_BR
17147 { 1085, 2, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #1085 = DS_GWS_SEMA_P
17148 { 1086, 2, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #1086 = DS_GWS_SEMA_RELEASE_ALL
17149 { 1087, 2, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #1087 = DS_GWS_SEMA_V
17150 { 1088, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1088 = DS_INC_RTN_U32
17152 { 1090, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1090 = DS_INC_RTN_U64
17154 { 1092, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1092 = DS_INC_SRC2_U32
17155 { 1093, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1093 = DS_INC_SRC2_U64
17156 { 1094, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1094 = DS_INC_U32
17158 { 1096, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1096 = DS_INC_U64
17160 { 1098, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1098 = DS_MAX_F32
17162 { 1100, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1100 = DS_MAX_F64
17164 { 1102, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1102 = DS_MAX_I32
17166 { 1104, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1104 = DS_MAX_I64
17168 { 1106, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1106 = DS_MAX_RTN_F32
17170 { 1108, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1108 = DS_MAX_RTN_F64
17172 { 1110, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1110 = DS_MAX_RTN_I32
17174 { 1112, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1112 = DS_MAX_RTN_I64
17176 { 1114, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1114 = DS_MAX_RTN_U32
17178 { 1116, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1116 = DS_MAX_RTN_U64
17180 { 1118, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1118 = DS_MAX_SRC2_F32
17181 { 1119, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1119 = DS_MAX_SRC2_F64
17182 { 1120, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1120 = DS_MAX_SRC2_I32
17183 { 1121, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1121 = DS_MAX_SRC2_I64
17184 { 1122, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1122 = DS_MAX_SRC2_U32
17185 { 1123, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1123 = DS_MAX_SRC2_U64
17186 { 1124, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1124 = DS_MAX_U32
17188 { 1126, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1126 = DS_MAX_U64
17190 { 1128, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1128 = DS_MIN_F32
17192 { 1130, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1130 = DS_MIN_F64
17194 { 1132, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1132 = DS_MIN_I32
17196 { 1134, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1134 = DS_MIN_I64
17198 { 1136, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1136 = DS_MIN_RTN_F32
17200 { 1138, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1138 = DS_MIN_RTN_F64
17202 { 1140, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1140 = DS_MIN_RTN_I32
17204 { 1142, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1142 = DS_MIN_RTN_I64
17206 { 1144, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1144 = DS_MIN_RTN_U32
17208 { 1146, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1146 = DS_MIN_RTN_U64
17210 { 1148, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1148 = DS_MIN_SRC2_F32
17211 { 1149, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1149 = DS_MIN_SRC2_F64
17212 { 1150, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1150 = DS_MIN_SRC2_I32
17213 { 1151, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1151 = DS_MIN_SRC2_I64
17214 { 1152, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1152 = DS_MIN_SRC2_U32
17215 { 1153, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1153 = DS_MIN_SRC2_U64
17216 { 1154, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1154 = DS_MIN_U32
17218 { 1156, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1156 = DS_MIN_U64
17220 { 1158, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1158 = DS_MSKOR_B32
17222 { 1160, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1160 = DS_MSKOR_B64
17224 { 1162, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1162 = DS_MSKOR_RTN_B32
17226 { 1164, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #1164 = DS_MSKOR_RTN_B64
17228 { 1166, 0, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x80400400000ULL, ImplicitList4, nullptr, nullptr, -1 ,nullptr }, // Inst #1166 = DS_NOP
17229 { 1167, 3, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1167 = DS_ORDERED_COUNT
17230 { 1168, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1168 = DS_OR_B32
17232 { 1170, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1170 = DS_OR_B64
17234 { 1172, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1172 = DS_OR_RTN_B32
17236 { 1174, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1174 = DS_OR_RTN_B64
17238 { 1176, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1176 = DS_OR_SRC2_B32
17239 { 1177, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1177 = DS_OR_SRC2_B64
17241 { 1179, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #1179 = DS_READ2ST64_B32
17243 { 1181, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1181 = DS_READ2ST64_B64
17245 { 1183, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #1183 = DS_READ2_B32
17247 { 1185, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1185 = DS_READ2_B64
17249 { 1187, 3, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1187 = DS_READ_ADDTID_B32
17250 { 1188, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1188 = DS_READ_B128
17252 { 1190, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1190 = DS_READ_B32
17254 { 1192, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1192 = DS_READ_B64
17256 { 1194, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #1194 = DS_READ_B96
17258 { 1196, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1196 = DS_READ_I16
17260 { 1198, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1198 = DS_READ_I8
17264 { 1202, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1202 = DS_READ_U16
17268 { 1206, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1206 = DS_READ_U8
17272 { 1210, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1210 = DS_RSUB_RTN_U32
17274 { 1212, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1212 = DS_RSUB_RTN_U64
17276 { 1214, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1214 = DS_RSUB_SRC2_U32
17277 { 1215, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1215 = DS_RSUB_SRC2_U64
17278 { 1216, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1216 = DS_RSUB_U32
17280 { 1218, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1218 = DS_RSUB_U64
17282 { 1220, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1220 = DS_SUB_RTN_U32
17284 { 1222, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1222 = DS_SUB_RTN_U64
17286 { 1224, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1224 = DS_SUB_SRC2_U32
17287 { 1225, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1225 = DS_SUB_SRC2_U64
17288 { 1226, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1226 = DS_SUB_U32
17290 { 1228, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1228 = DS_SUB_U64
17293 { 1231, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1231 = DS_WRAP_RTN_B32
17295 { 1233, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #1233 = DS_WRITE2ST64_B32
17297 { 1235, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #1235 = DS_WRITE2ST64_B64
17299 { 1237, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #1237 = DS_WRITE2_B32
17301 { 1239, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #1239 = DS_WRITE2_B64
17303 { 1241, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1241 = DS_WRITE_ADDTID_B32
17304 { 1242, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1242 = DS_WRITE_B128
17306 { 1244, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1244 = DS_WRITE_B16
17309 { 1247, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1247 = DS_WRITE_B32
17311 { 1249, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1249 = DS_WRITE_B64
17313 { 1251, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1251 = DS_WRITE_B8
17316 { 1254, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1254 = DS_WRITE_B96
17318 { 1256, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1256 = DS_WRITE_SRC2_B32
17319 { 1257, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1257 = DS_WRITE_SRC2_B64
17320 { 1258, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1258 = DS_WRXCHG2ST64_RTN_B32
17322 { 1260, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1260 = DS_WRXCHG2ST64_RTN_B64
17324 { 1262, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1262 = DS_WRXCHG2_RTN_B32
17326 { 1264, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1264 = DS_WRXCHG2_RTN_B64
17328 { 1266, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1266 = DS_WRXCHG_RTN_B32
17330 { 1268, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1268 = DS_WRXCHG_RTN_B64
17332 { 1270, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1270 = DS_XOR_B32
17334 { 1272, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1272 = DS_XOR_B64
17336 { 1274, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1274 = DS_XOR_RTN_B32
17338 { 1276, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1276 = DS_XOR_RTN_B64
17340 { 1278, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1278 = DS_XOR_SRC2_B32
17341 { 1279, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1279 = DS_XOR_SRC2_B64
19716 { 3654, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo386, -1 ,nullptr }, // Inst #3654 = V_INTERP_MOV_F32
19717 { 3655, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo387, -1 ,nullptr }, // Inst #3655 = V_INTERP_MOV_F32_e64
19718 { 3656, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList4, nullptr, OperandInfo388, -1 ,nullptr }, // Inst #3656 = V_INTERP_P1LL_F16
19719 { 3657, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList4, nullptr, OperandInfo389, -1 ,nullptr }, // Inst #3657 = V_INTERP_P1LV_F16
19720 { 3658, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #3658 = V_INTERP_P1_F32
19721 { 3659, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo390, -1 ,nullptr }, // Inst #3659 = V_INTERP_P1_F32_16bank
19722 { 3660, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo391, -1 ,nullptr }, // Inst #3660 = V_INTERP_P1_F32_e64
19723 { 3661, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10b00000000402ULL, ImplicitList4, nullptr, OperandInfo392, -1 ,nullptr }, // Inst #3661 = V_INTERP_P2_F16
19725 { 3663, 5, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #3663 = V_INTERP_P2_F32
19726 { 3664, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo391, -1 ,nullptr }, // Inst #3664 = V_INTERP_P2_F32_e64
19914 { 3852, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo411, -1 ,nullptr }, // Inst #3852 = V_MOVRELD_B32_V1
19915 { 3853, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo412, -1 ,nullptr }, // Inst #3853 = V_MOVRELD_B32_V16
19916 { 3854, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #3854 = V_MOVRELD_B32_V2
19917 { 3855, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo414, -1 ,nullptr }, // Inst #3855 = V_MOVRELD_B32_V4
19918 { 3856, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo415, -1 ,nullptr }, // Inst #3856 = V_MOVRELD_B32_V8
19919 { 3857, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3857 = V_MOVRELD_B32_e32
19920 { 3858, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3858 = V_MOVRELD_B32_e64
19923 { 3861, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3861 = V_MOVRELSD_B32_e32
19924 { 3862, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3862 = V_MOVRELSD_B32_e64
19925 { 3863, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo416, -1 ,nullptr }, // Inst #3863 = V_MOVRELS_B32_e32
19926 { 3864, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList4, nullptr, OperandInfo416, -1 ,nullptr }, // Inst #3864 = V_MOVRELS_B32_e64
30298 { 14236, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo387, -1 ,nullptr }, // Inst #14236 = V_INTERP_MOV_F32_e64_gfx10
30299 { 14237, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo387, -1 ,nullptr }, // Inst #14237 = V_INTERP_MOV_F32_e64_vi
30300 { 14238, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo386, -1 ,nullptr }, // Inst #14238 = V_INTERP_MOV_F32_gfx10
30301 { 14239, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo386, -1 ,nullptr }, // Inst #14239 = V_INTERP_MOV_F32_si
30302 { 14240, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo386, -1 ,nullptr }, // Inst #14240 = V_INTERP_MOV_F32_vi
30303 { 14241, 8, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList4, nullptr, OperandInfo388, -1 ,nullptr }, // Inst #14241 = V_INTERP_P1LL_F16_gfx10
30304 { 14242, 8, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList4, nullptr, OperandInfo388, -1 ,nullptr }, // Inst #14242 = V_INTERP_P1LL_F16_vi
30305 { 14243, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList4, nullptr, OperandInfo389, -1 ,nullptr }, // Inst #14243 = V_INTERP_P1LV_F16_gfx10
30306 { 14244, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList4, nullptr, OperandInfo389, -1 ,nullptr }, // Inst #14244 = V_INTERP_P1LV_F16_vi
30307 { 14245, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo390, -1 ,nullptr }, // Inst #14245 = V_INTERP_P1_F32_16bank_gfx10
30308 { 14246, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo390, -1 ,nullptr }, // Inst #14246 = V_INTERP_P1_F32_16bank_si
30309 { 14247, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo390, -1 ,nullptr }, // Inst #14247 = V_INTERP_P1_F32_16bank_vi
30310 { 14248, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo391, -1 ,nullptr }, // Inst #14248 = V_INTERP_P1_F32_e64_gfx10
30311 { 14249, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo391, -1 ,nullptr }, // Inst #14249 = V_INTERP_P1_F32_e64_vi
30312 { 14250, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #14250 = V_INTERP_P1_F32_gfx10
30313 { 14251, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #14251 = V_INTERP_P1_F32_si
30314 { 14252, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #14252 = V_INTERP_P1_F32_vi
30315 { 14253, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10b00000000402ULL, ImplicitList4, nullptr, OperandInfo392, -1 ,nullptr }, // Inst #14253 = V_INTERP_P2_F16_gfx10
30317 { 14255, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10b00000000402ULL, ImplicitList4, nullptr, OperandInfo392, -1 ,nullptr }, // Inst #14255 = V_INTERP_P2_F16_vi
30318 { 14256, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo391, -1 ,nullptr }, // Inst #14256 = V_INTERP_P2_F32_e64_gfx10
30319 { 14257, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo391, -1 ,nullptr }, // Inst #14257 = V_INTERP_P2_F32_e64_vi
30320 { 14258, 5, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14258 = V_INTERP_P2_F32_gfx10
30321 { 14259, 5, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14259 = V_INTERP_P2_F32_si
30322 { 14260, 5, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14260 = V_INTERP_P2_F32_vi
30323 { 14261, 9, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x10b00000000402ULL, ImplicitList4, nullptr, OperandInfo392, -1 ,nullptr }, // Inst #14261 = V_INTERP_P2_LEGACY_F16_gfx9
30689 { 14627, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14627 = V_MOVRELD_B32_e32_gfx10
30690 { 14628, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14628 = V_MOVRELD_B32_e32_gfx6_gfx7
30691 { 14629, 2, 0, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14629 = V_MOVRELD_B32_e32_vi
30692 { 14630, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14630 = V_MOVRELD_B32_e64_gfx10
30693 { 14631, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14631 = V_MOVRELD_B32_e64_gfx6_gfx7
30694 { 14632, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14632 = V_MOVRELD_B32_e64_vi
30697 { 14635, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14635 = V_MOVRELSD_B32_e32_gfx10
30698 { 14636, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14636 = V_MOVRELSD_B32_e32_gfx6_gfx7
30699 { 14637, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14637 = V_MOVRELSD_B32_e32_vi
30700 { 14638, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14638 = V_MOVRELSD_B32_e64_gfx10
30701 { 14639, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14639 = V_MOVRELSD_B32_e64_gfx6_gfx7
30702 { 14640, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #14640 = V_MOVRELSD_B32_e64_vi
30703 { 14641, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo416, -1 ,nullptr }, // Inst #14641 = V_MOVRELS_B32_e32_gfx10
30704 { 14642, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo416, -1 ,nullptr }, // Inst #14642 = V_MOVRELS_B32_e32_gfx6_gfx7
30705 { 14643, 2, 1, 4, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x82ULL, ImplicitList4, nullptr, OperandInfo416, -1 ,nullptr }, // Inst #14643 = V_MOVRELS_B32_e32_vi
30706 { 14644, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo416, -1 ,nullptr }, // Inst #14644 = V_MOVRELS_B32_e64_gfx10
30707 { 14645, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo416, -1 ,nullptr }, // Inst #14645 = V_MOVRELS_B32_e64_gfx6_gfx7
30708 { 14646, 2, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x402ULL, ImplicitList4, nullptr, OperandInfo416, -1 ,nullptr }, // Inst #14646 = V_MOVRELS_B32_e64_vi