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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16576 { 514, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #514 = BUFFER_LOAD_DWORDX2_LDS_ADDR64
16577 { 515, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #515 = BUFFER_LOAD_DWORDX2_LDS_BOTHEN
16578 { 516, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #516 = BUFFER_LOAD_DWORDX2_LDS_BOTHEN_exact
16579 { 517, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #517 = BUFFER_LOAD_DWORDX2_LDS_IDXEN
16580 { 518, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #518 = BUFFER_LOAD_DWORDX2_LDS_IDXEN_exact
16581 { 519, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #519 = BUFFER_LOAD_DWORDX2_LDS_OFFEN
16582 { 520, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #520 = BUFFER_LOAD_DWORDX2_LDS_OFFEN_exact
16583 { 521, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #521 = BUFFER_LOAD_DWORDX2_LDS_OFFSET
16584 { 522, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #522 = BUFFER_LOAD_DWORDX2_LDS_OFFSET_exact
16594 { 532, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #532 = BUFFER_LOAD_DWORDX3_LDS_ADDR64
16595 { 533, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #533 = BUFFER_LOAD_DWORDX3_LDS_BOTHEN
16596 { 534, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #534 = BUFFER_LOAD_DWORDX3_LDS_BOTHEN_exact
16597 { 535, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #535 = BUFFER_LOAD_DWORDX3_LDS_IDXEN
16598 { 536, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #536 = BUFFER_LOAD_DWORDX3_LDS_IDXEN_exact
16599 { 537, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #537 = BUFFER_LOAD_DWORDX3_LDS_OFFEN
16600 { 538, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #538 = BUFFER_LOAD_DWORDX3_LDS_OFFEN_exact
16601 { 539, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #539 = BUFFER_LOAD_DWORDX3_LDS_OFFSET
16602 { 540, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #540 = BUFFER_LOAD_DWORDX3_LDS_OFFSET_exact
16612 { 550, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #550 = BUFFER_LOAD_DWORDX4_LDS_ADDR64
16613 { 551, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #551 = BUFFER_LOAD_DWORDX4_LDS_BOTHEN
16614 { 552, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #552 = BUFFER_LOAD_DWORDX4_LDS_BOTHEN_exact
16615 { 553, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #553 = BUFFER_LOAD_DWORDX4_LDS_IDXEN
16616 { 554, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #554 = BUFFER_LOAD_DWORDX4_LDS_IDXEN_exact
16617 { 555, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #555 = BUFFER_LOAD_DWORDX4_LDS_OFFEN
16618 { 556, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #556 = BUFFER_LOAD_DWORDX4_LDS_OFFEN_exact
16619 { 557, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #557 = BUFFER_LOAD_DWORDX4_LDS_OFFSET
16620 { 558, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #558 = BUFFER_LOAD_DWORDX4_LDS_OFFSET_exact
16630 { 568, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #568 = BUFFER_LOAD_DWORD_LDS_ADDR64
16631 { 569, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #569 = BUFFER_LOAD_DWORD_LDS_BOTHEN
16632 { 570, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #570 = BUFFER_LOAD_DWORD_LDS_BOTHEN_exact
16633 { 571, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #571 = BUFFER_LOAD_DWORD_LDS_IDXEN
16634 { 572, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #572 = BUFFER_LOAD_DWORD_LDS_IDXEN_exact
16635 { 573, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #573 = BUFFER_LOAD_DWORD_LDS_OFFEN
16636 { 574, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #574 = BUFFER_LOAD_DWORD_LDS_OFFEN_exact
16637 { 575, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #575 = BUFFER_LOAD_DWORD_LDS_OFFSET
16638 { 576, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #576 = BUFFER_LOAD_DWORD_LDS_OFFSET_exact
16756 { 694, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #694 = BUFFER_LOAD_FORMAT_X_LDS_ADDR64
16757 { 695, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #695 = BUFFER_LOAD_FORMAT_X_LDS_BOTHEN
16758 { 696, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #696 = BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_exact
16759 { 697, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #697 = BUFFER_LOAD_FORMAT_X_LDS_IDXEN
16760 { 698, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #698 = BUFFER_LOAD_FORMAT_X_LDS_IDXEN_exact
16761 { 699, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #699 = BUFFER_LOAD_FORMAT_X_LDS_OFFEN
16762 { 700, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #700 = BUFFER_LOAD_FORMAT_X_LDS_OFFEN_exact
16763 { 701, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #701 = BUFFER_LOAD_FORMAT_X_LDS_OFFSET
16764 { 702, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #702 = BUFFER_LOAD_FORMAT_X_LDS_OFFSET_exact
16792 { 730, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #730 = BUFFER_LOAD_SBYTE_LDS_ADDR64
16793 { 731, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #731 = BUFFER_LOAD_SBYTE_LDS_BOTHEN
16794 { 732, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #732 = BUFFER_LOAD_SBYTE_LDS_BOTHEN_exact
16795 { 733, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #733 = BUFFER_LOAD_SBYTE_LDS_IDXEN
16796 { 734, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #734 = BUFFER_LOAD_SBYTE_LDS_IDXEN_exact
16797 { 735, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #735 = BUFFER_LOAD_SBYTE_LDS_OFFEN
16798 { 736, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #736 = BUFFER_LOAD_SBYTE_LDS_OFFEN_exact
16799 { 737, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #737 = BUFFER_LOAD_SBYTE_LDS_OFFSET
16800 { 738, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #738 = BUFFER_LOAD_SBYTE_LDS_OFFSET_exact
16828 { 766, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #766 = BUFFER_LOAD_SSHORT_LDS_ADDR64
16829 { 767, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #767 = BUFFER_LOAD_SSHORT_LDS_BOTHEN
16830 { 768, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #768 = BUFFER_LOAD_SSHORT_LDS_BOTHEN_exact
16831 { 769, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #769 = BUFFER_LOAD_SSHORT_LDS_IDXEN
16832 { 770, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #770 = BUFFER_LOAD_SSHORT_LDS_IDXEN_exact
16833 { 771, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #771 = BUFFER_LOAD_SSHORT_LDS_OFFEN
16834 { 772, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #772 = BUFFER_LOAD_SSHORT_LDS_OFFEN_exact
16835 { 773, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #773 = BUFFER_LOAD_SSHORT_LDS_OFFSET
16836 { 774, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #774 = BUFFER_LOAD_SSHORT_LDS_OFFSET_exact
16864 { 802, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #802 = BUFFER_LOAD_UBYTE_LDS_ADDR64
16865 { 803, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #803 = BUFFER_LOAD_UBYTE_LDS_BOTHEN
16866 { 804, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #804 = BUFFER_LOAD_UBYTE_LDS_BOTHEN_exact
16867 { 805, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #805 = BUFFER_LOAD_UBYTE_LDS_IDXEN
16868 { 806, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #806 = BUFFER_LOAD_UBYTE_LDS_IDXEN_exact
16869 { 807, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #807 = BUFFER_LOAD_UBYTE_LDS_OFFEN
16870 { 808, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #808 = BUFFER_LOAD_UBYTE_LDS_OFFEN_exact
16871 { 809, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #809 = BUFFER_LOAD_UBYTE_LDS_OFFSET
16872 { 810, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #810 = BUFFER_LOAD_UBYTE_LDS_OFFSET_exact
16882 { 820, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #820 = BUFFER_LOAD_USHORT_LDS_ADDR64
16883 { 821, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #821 = BUFFER_LOAD_USHORT_LDS_BOTHEN
16884 { 822, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #822 = BUFFER_LOAD_USHORT_LDS_BOTHEN_exact
16885 { 823, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #823 = BUFFER_LOAD_USHORT_LDS_IDXEN
16886 { 824, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #824 = BUFFER_LOAD_USHORT_LDS_IDXEN_exact
16887 { 825, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #825 = BUFFER_LOAD_USHORT_LDS_OFFEN
16888 { 826, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #826 = BUFFER_LOAD_USHORT_LDS_OFFEN_exact
16889 { 827, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #827 = BUFFER_LOAD_USHORT_LDS_OFFSET
16890 { 828, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #828 = BUFFER_LOAD_USHORT_LDS_OFFSET_exact
17066 { 1004, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1004 = BUFFER_STORE_LDS_DWORD
27670 { 11608, 1, 0, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x41ULL, ImplicitList3, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #11608 = S_SENDMSG
27671 { 11609, 1, 0, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x41ULL, ImplicitList3, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #11609 = S_SENDMSGHALT