reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

18382   { 2320,	8,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #2320 = V_ADDC_U32_dpp
18383   { 2321,	3,	1,	4,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #2321 = V_ADDC_U32_e32
18385   { 2323,	10,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #2323 = V_ADDC_U32_sdwa
18396   { 2334,	8,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #2334 = V_ADD_I32_dpp
18397   { 2335,	3,	1,	4,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #2335 = V_ADD_I32_e32
18400   { 2338,	10,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #2338 = V_ADD_I32_sdwa
18614   { 2552,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2552 = V_CMPS_EQ_F32_e32
18616   { 2554,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2554 = V_CMPS_EQ_F32_sdwa
18617   { 2555,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2555 = V_CMPS_EQ_F64_e32
18619   { 2557,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2557 = V_CMPS_F_F32_e32
18621   { 2559,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2559 = V_CMPS_F_F32_sdwa
18622   { 2560,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2560 = V_CMPS_F_F64_e32
18624   { 2562,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2562 = V_CMPS_GE_F32_e32
18626   { 2564,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2564 = V_CMPS_GE_F32_sdwa
18627   { 2565,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2565 = V_CMPS_GE_F64_e32
18629   { 2567,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2567 = V_CMPS_GT_F32_e32
18631   { 2569,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2569 = V_CMPS_GT_F32_sdwa
18632   { 2570,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2570 = V_CMPS_GT_F64_e32
18634   { 2572,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2572 = V_CMPS_LE_F32_e32
18636   { 2574,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2574 = V_CMPS_LE_F32_sdwa
18637   { 2575,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2575 = V_CMPS_LE_F64_e32
18639   { 2577,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2577 = V_CMPS_LG_F32_e32
18641   { 2579,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2579 = V_CMPS_LG_F32_sdwa
18642   { 2580,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2580 = V_CMPS_LG_F64_e32
18644   { 2582,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2582 = V_CMPS_LT_F32_e32
18646   { 2584,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2584 = V_CMPS_LT_F32_sdwa
18647   { 2585,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2585 = V_CMPS_LT_F64_e32
18649   { 2587,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2587 = V_CMPS_NEQ_F32_e32
18651   { 2589,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2589 = V_CMPS_NEQ_F32_sdwa
18652   { 2590,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2590 = V_CMPS_NEQ_F64_e32
18654   { 2592,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2592 = V_CMPS_NGE_F32_e32
18656   { 2594,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2594 = V_CMPS_NGE_F32_sdwa
18657   { 2595,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2595 = V_CMPS_NGE_F64_e32
18659   { 2597,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2597 = V_CMPS_NGT_F32_e32
18661   { 2599,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2599 = V_CMPS_NGT_F32_sdwa
18662   { 2600,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2600 = V_CMPS_NGT_F64_e32
18664   { 2602,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2602 = V_CMPS_NLE_F32_e32
18666   { 2604,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2604 = V_CMPS_NLE_F32_sdwa
18667   { 2605,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2605 = V_CMPS_NLE_F64_e32
18669   { 2607,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2607 = V_CMPS_NLG_F32_e32
18671   { 2609,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2609 = V_CMPS_NLG_F32_sdwa
18672   { 2610,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2610 = V_CMPS_NLG_F64_e32
18674   { 2612,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2612 = V_CMPS_NLT_F32_e32
18676   { 2614,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2614 = V_CMPS_NLT_F32_sdwa
18677   { 2615,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2615 = V_CMPS_NLT_F64_e32
18679   { 2617,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2617 = V_CMPS_O_F32_e32
18681   { 2619,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2619 = V_CMPS_O_F32_sdwa
18682   { 2620,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2620 = V_CMPS_O_F64_e32
18684   { 2622,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2622 = V_CMPS_TRU_F32_e32
18686   { 2624,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2624 = V_CMPS_TRU_F32_sdwa
18687   { 2625,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2625 = V_CMPS_TRU_F64_e32
18689   { 2627,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #2627 = V_CMPS_U_F32_e32
18691   { 2629,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #2629 = V_CMPS_U_F32_sdwa
18692   { 2630,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #2630 = V_CMPS_U_F64_e32
19222   { 3160,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3160 = V_CMP_CLASS_F16_e32
19224   { 3162,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3162 = V_CMP_CLASS_F16_sdwa
19225   { 3163,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3163 = V_CMP_CLASS_F32_e32
19227   { 3165,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3165 = V_CMP_CLASS_F32_sdwa
19228   { 3166,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo325, -1 ,nullptr },  // Inst #3166 = V_CMP_CLASS_F64_e32
19230   { 3168,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3168 = V_CMP_EQ_F16_e32
19232   { 3170,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3170 = V_CMP_EQ_F16_sdwa
19233   { 3171,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3171 = V_CMP_EQ_F32_e32
19235   { 3173,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3173 = V_CMP_EQ_F32_sdwa
19236   { 3174,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3174 = V_CMP_EQ_F64_e32
19238   { 3176,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3176 = V_CMP_EQ_I16_e32
19240   { 3178,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3178 = V_CMP_EQ_I16_sdwa
19241   { 3179,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3179 = V_CMP_EQ_I32_e32
19243   { 3181,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3181 = V_CMP_EQ_I32_sdwa
19244   { 3182,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3182 = V_CMP_EQ_I64_e32
19246   { 3184,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3184 = V_CMP_EQ_U16_e32
19248   { 3186,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3186 = V_CMP_EQ_U16_sdwa
19249   { 3187,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3187 = V_CMP_EQ_U32_e32
19251   { 3189,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3189 = V_CMP_EQ_U32_sdwa
19252   { 3190,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3190 = V_CMP_EQ_U64_e32
19254   { 3192,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3192 = V_CMP_F_F16_e32
19256   { 3194,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3194 = V_CMP_F_F16_sdwa
19257   { 3195,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3195 = V_CMP_F_F32_e32
19259   { 3197,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3197 = V_CMP_F_F32_sdwa
19260   { 3198,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3198 = V_CMP_F_F64_e32
19262   { 3200,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3200 = V_CMP_F_I16_e32
19264   { 3202,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3202 = V_CMP_F_I16_sdwa
19265   { 3203,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3203 = V_CMP_F_I32_e32
19267   { 3205,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3205 = V_CMP_F_I32_sdwa
19268   { 3206,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3206 = V_CMP_F_I64_e32
19270   { 3208,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3208 = V_CMP_F_U16_e32
19272   { 3210,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3210 = V_CMP_F_U16_sdwa
19273   { 3211,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3211 = V_CMP_F_U32_e32
19275   { 3213,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3213 = V_CMP_F_U32_sdwa
19276   { 3214,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3214 = V_CMP_F_U64_e32
19278   { 3216,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3216 = V_CMP_GE_F16_e32
19280   { 3218,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3218 = V_CMP_GE_F16_sdwa
19281   { 3219,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3219 = V_CMP_GE_F32_e32
19283   { 3221,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3221 = V_CMP_GE_F32_sdwa
19284   { 3222,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3222 = V_CMP_GE_F64_e32
19286   { 3224,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3224 = V_CMP_GE_I16_e32
19288   { 3226,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3226 = V_CMP_GE_I16_sdwa
19289   { 3227,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3227 = V_CMP_GE_I32_e32
19291   { 3229,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3229 = V_CMP_GE_I32_sdwa
19292   { 3230,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3230 = V_CMP_GE_I64_e32
19294   { 3232,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3232 = V_CMP_GE_U16_e32
19296   { 3234,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3234 = V_CMP_GE_U16_sdwa
19297   { 3235,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3235 = V_CMP_GE_U32_e32
19299   { 3237,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3237 = V_CMP_GE_U32_sdwa
19300   { 3238,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3238 = V_CMP_GE_U64_e32
19302   { 3240,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3240 = V_CMP_GT_F16_e32
19304   { 3242,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3242 = V_CMP_GT_F16_sdwa
19305   { 3243,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3243 = V_CMP_GT_F32_e32
19307   { 3245,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3245 = V_CMP_GT_F32_sdwa
19308   { 3246,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3246 = V_CMP_GT_F64_e32
19310   { 3248,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3248 = V_CMP_GT_I16_e32
19312   { 3250,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3250 = V_CMP_GT_I16_sdwa
19313   { 3251,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3251 = V_CMP_GT_I32_e32
19315   { 3253,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3253 = V_CMP_GT_I32_sdwa
19316   { 3254,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3254 = V_CMP_GT_I64_e32
19318   { 3256,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3256 = V_CMP_GT_U16_e32
19320   { 3258,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3258 = V_CMP_GT_U16_sdwa
19321   { 3259,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3259 = V_CMP_GT_U32_e32
19323   { 3261,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3261 = V_CMP_GT_U32_sdwa
19324   { 3262,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3262 = V_CMP_GT_U64_e32
19326   { 3264,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3264 = V_CMP_LE_F16_e32
19328   { 3266,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3266 = V_CMP_LE_F16_sdwa
19329   { 3267,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3267 = V_CMP_LE_F32_e32
19331   { 3269,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3269 = V_CMP_LE_F32_sdwa
19332   { 3270,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3270 = V_CMP_LE_F64_e32
19334   { 3272,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3272 = V_CMP_LE_I16_e32
19336   { 3274,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3274 = V_CMP_LE_I16_sdwa
19337   { 3275,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3275 = V_CMP_LE_I32_e32
19339   { 3277,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3277 = V_CMP_LE_I32_sdwa
19340   { 3278,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3278 = V_CMP_LE_I64_e32
19342   { 3280,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3280 = V_CMP_LE_U16_e32
19344   { 3282,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3282 = V_CMP_LE_U16_sdwa
19345   { 3283,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3283 = V_CMP_LE_U32_e32
19347   { 3285,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3285 = V_CMP_LE_U32_sdwa
19348   { 3286,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3286 = V_CMP_LE_U64_e32
19350   { 3288,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3288 = V_CMP_LG_F16_e32
19352   { 3290,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3290 = V_CMP_LG_F16_sdwa
19353   { 3291,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3291 = V_CMP_LG_F32_e32
19355   { 3293,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3293 = V_CMP_LG_F32_sdwa
19356   { 3294,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3294 = V_CMP_LG_F64_e32
19358   { 3296,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3296 = V_CMP_LT_F16_e32
19360   { 3298,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3298 = V_CMP_LT_F16_sdwa
19361   { 3299,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3299 = V_CMP_LT_F32_e32
19363   { 3301,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3301 = V_CMP_LT_F32_sdwa
19364   { 3302,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3302 = V_CMP_LT_F64_e32
19366   { 3304,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3304 = V_CMP_LT_I16_e32
19368   { 3306,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3306 = V_CMP_LT_I16_sdwa
19369   { 3307,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3307 = V_CMP_LT_I32_e32
19371   { 3309,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3309 = V_CMP_LT_I32_sdwa
19372   { 3310,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3310 = V_CMP_LT_I64_e32
19374   { 3312,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3312 = V_CMP_LT_U16_e32
19376   { 3314,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3314 = V_CMP_LT_U16_sdwa
19377   { 3315,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3315 = V_CMP_LT_U32_e32
19379   { 3317,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3317 = V_CMP_LT_U32_sdwa
19380   { 3318,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3318 = V_CMP_LT_U64_e32
19382   { 3320,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3320 = V_CMP_NEQ_F16_e32
19384   { 3322,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3322 = V_CMP_NEQ_F16_sdwa
19385   { 3323,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3323 = V_CMP_NEQ_F32_e32
19387   { 3325,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3325 = V_CMP_NEQ_F32_sdwa
19388   { 3326,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3326 = V_CMP_NEQ_F64_e32
19390   { 3328,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3328 = V_CMP_NE_I16_e32
19392   { 3330,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3330 = V_CMP_NE_I16_sdwa
19393   { 3331,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3331 = V_CMP_NE_I32_e32
19395   { 3333,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3333 = V_CMP_NE_I32_sdwa
19396   { 3334,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3334 = V_CMP_NE_I64_e32
19398   { 3336,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3336 = V_CMP_NE_U16_e32
19400   { 3338,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3338 = V_CMP_NE_U16_sdwa
19401   { 3339,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3339 = V_CMP_NE_U32_e32
19403   { 3341,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3341 = V_CMP_NE_U32_sdwa
19404   { 3342,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3342 = V_CMP_NE_U64_e32
19406   { 3344,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3344 = V_CMP_NGE_F16_e32
19408   { 3346,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3346 = V_CMP_NGE_F16_sdwa
19409   { 3347,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3347 = V_CMP_NGE_F32_e32
19411   { 3349,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3349 = V_CMP_NGE_F32_sdwa
19412   { 3350,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3350 = V_CMP_NGE_F64_e32
19414   { 3352,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3352 = V_CMP_NGT_F16_e32
19416   { 3354,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3354 = V_CMP_NGT_F16_sdwa
19417   { 3355,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3355 = V_CMP_NGT_F32_e32
19419   { 3357,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3357 = V_CMP_NGT_F32_sdwa
19420   { 3358,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3358 = V_CMP_NGT_F64_e32
19422   { 3360,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3360 = V_CMP_NLE_F16_e32
19424   { 3362,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3362 = V_CMP_NLE_F16_sdwa
19425   { 3363,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3363 = V_CMP_NLE_F32_e32
19427   { 3365,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3365 = V_CMP_NLE_F32_sdwa
19428   { 3366,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3366 = V_CMP_NLE_F64_e32
19430   { 3368,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3368 = V_CMP_NLG_F16_e32
19432   { 3370,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3370 = V_CMP_NLG_F16_sdwa
19433   { 3371,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3371 = V_CMP_NLG_F32_e32
19435   { 3373,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3373 = V_CMP_NLG_F32_sdwa
19436   { 3374,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3374 = V_CMP_NLG_F64_e32
19438   { 3376,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3376 = V_CMP_NLT_F16_e32
19440   { 3378,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3378 = V_CMP_NLT_F16_sdwa
19441   { 3379,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3379 = V_CMP_NLT_F32_e32
19443   { 3381,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3381 = V_CMP_NLT_F32_sdwa
19444   { 3382,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3382 = V_CMP_NLT_F64_e32
19446   { 3384,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3384 = V_CMP_O_F16_e32
19448   { 3386,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3386 = V_CMP_O_F16_sdwa
19449   { 3387,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3387 = V_CMP_O_F32_e32
19451   { 3389,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3389 = V_CMP_O_F32_sdwa
19452   { 3390,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3390 = V_CMP_O_F64_e32
19454   { 3392,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3392 = V_CMP_TRU_F16_e32
19456   { 3394,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3394 = V_CMP_TRU_F16_sdwa
19457   { 3395,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3395 = V_CMP_TRU_F32_e32
19459   { 3397,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3397 = V_CMP_TRU_F32_sdwa
19460   { 3398,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3398 = V_CMP_TRU_F64_e32
19462   { 3400,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3400 = V_CMP_T_I16_e32
19464   { 3402,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3402 = V_CMP_T_I16_sdwa
19465   { 3403,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3403 = V_CMP_T_I32_e32
19467   { 3405,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3405 = V_CMP_T_I32_sdwa
19468   { 3406,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3406 = V_CMP_T_I64_e32
19470   { 3408,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #3408 = V_CMP_T_U16_e32
19472   { 3410,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #3410 = V_CMP_T_U16_sdwa
19473   { 3411,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #3411 = V_CMP_T_U32_e32
19475   { 3413,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #3413 = V_CMP_T_U32_sdwa
19476   { 3414,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #3414 = V_CMP_T_U64_e32
19478   { 3416,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #3416 = V_CMP_U_F16_e32
19480   { 3418,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #3418 = V_CMP_U_F16_sdwa
19481   { 3419,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #3419 = V_CMP_U_F32_e32
19483   { 3421,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #3421 = V_CMP_U_F32_sdwa
19484   { 3422,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #3422 = V_CMP_U_F64_e32
20109   { 4047,	8,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #4047 = V_SUBBREV_U32_dpp
20110   { 4048,	3,	1,	4,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #4048 = V_SUBBREV_U32_e32
20112   { 4050,	10,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #4050 = V_SUBBREV_U32_sdwa
20113   { 4051,	8,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #4051 = V_SUBB_U32_dpp
20114   { 4052,	3,	1,	4,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #4052 = V_SUBB_U32_e32
20116   { 4054,	10,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #4054 = V_SUBB_U32_sdwa
20125   { 4063,	8,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #4063 = V_SUBREV_I32_dpp
20126   { 4064,	3,	1,	4,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #4064 = V_SUBREV_I32_e32
20128   { 4066,	10,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #4066 = V_SUBREV_I32_sdwa
20146   { 4084,	8,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #4084 = V_SUB_I32_dpp
20147   { 4085,	3,	1,	4,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #4085 = V_SUB_I32_e32
20150   { 4088,	10,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #4088 = V_SUB_I32_sdwa
27343   { 11281,	1,	0,	4,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #11281 = S_CBRANCH_VCCNZ
27344   { 11282,	1,	0,	8,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #11282 = S_CBRANCH_VCCNZ_pad_s_nop
27345   { 11283,	1,	0,	4,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #11283 = S_CBRANCH_VCCZ
27346   { 11284,	1,	0,	8,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #11284 = S_CBRANCH_VCCZ_pad_s_nop
27964   { 11902,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #11902 = V_ADDC_CO_U32_dpp_gfx9
27965   { 11903,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11903 = V_ADDC_CO_U32_e32_gfx9
27967   { 11905,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11905 = V_ADDC_CO_U32_sdwa_gfx9
27968   { 11906,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #11906 = V_ADDC_U32_dpp_vi
27969   { 11907,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11907 = V_ADDC_U32_e32_gfx6_gfx7
27970   { 11908,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11908 = V_ADDC_U32_e32_vi
27973   { 11911,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11911 = V_ADDC_U32_sdwa_vi
27974   { 11912,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #11912 = V_ADD_CO_CI_U32_dpp8_gfx10
27975   { 11913,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #11913 = V_ADD_CO_CI_U32_dpp8_w32_gfx10
27976   { 11914,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #11914 = V_ADD_CO_CI_U32_dpp8_w64_gfx10
27977   { 11915,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #11915 = V_ADD_CO_CI_U32_dpp_gfx10
27978   { 11916,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #11916 = V_ADD_CO_CI_U32_dpp_w32_gfx10
27979   { 11917,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #11917 = V_ADD_CO_CI_U32_dpp_w64_gfx10
27980   { 11918,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11918 = V_ADD_CO_CI_U32_e32_gfx10
27982   { 11920,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11920 = V_ADD_CO_CI_U32_sdwa_gfx10
27983   { 11921,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11921 = V_ADD_CO_CI_U32_sdwa_w32_gfx10
27984   { 11922,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11922 = V_ADD_CO_CI_U32_sdwa_w64_gfx10
27985   { 11923,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #11923 = V_ADD_CO_U32_dpp_gfx9
27986   { 11924,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11924 = V_ADD_CO_U32_e32_gfx9
27989   { 11927,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11927 = V_ADD_CO_U32_sdwa_gfx9
28016   { 11954,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11954 = V_ADD_I32_e32_gfx6_gfx7
28035   { 11973,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #11973 = V_ADD_U32_dpp_vi
28037   { 11975,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11975 = V_ADD_U32_e32_vi
28041   { 11979,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11979 = V_ADD_U32_sdwa_vi
28212   { 12150,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12150 = V_CMPS_EQ_F32_e32_gfx6_gfx7
28214   { 12152,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12152 = V_CMPS_EQ_F64_e32_gfx6_gfx7
28216   { 12154,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12154 = V_CMPS_F_F32_e32_gfx6_gfx7
28218   { 12156,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12156 = V_CMPS_F_F64_e32_gfx6_gfx7
28220   { 12158,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12158 = V_CMPS_GE_F32_e32_gfx6_gfx7
28222   { 12160,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12160 = V_CMPS_GE_F64_e32_gfx6_gfx7
28224   { 12162,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12162 = V_CMPS_GT_F32_e32_gfx6_gfx7
28226   { 12164,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12164 = V_CMPS_GT_F64_e32_gfx6_gfx7
28228   { 12166,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12166 = V_CMPS_LE_F32_e32_gfx6_gfx7
28230   { 12168,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12168 = V_CMPS_LE_F64_e32_gfx6_gfx7
28232   { 12170,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12170 = V_CMPS_LG_F32_e32_gfx6_gfx7
28234   { 12172,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12172 = V_CMPS_LG_F64_e32_gfx6_gfx7
28236   { 12174,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12174 = V_CMPS_LT_F32_e32_gfx6_gfx7
28238   { 12176,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12176 = V_CMPS_LT_F64_e32_gfx6_gfx7
28240   { 12178,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12178 = V_CMPS_NEQ_F32_e32_gfx6_gfx7
28242   { 12180,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12180 = V_CMPS_NEQ_F64_e32_gfx6_gfx7
28244   { 12182,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12182 = V_CMPS_NGE_F32_e32_gfx6_gfx7
28246   { 12184,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12184 = V_CMPS_NGE_F64_e32_gfx6_gfx7
28248   { 12186,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12186 = V_CMPS_NGT_F32_e32_gfx6_gfx7
28250   { 12188,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12188 = V_CMPS_NGT_F64_e32_gfx6_gfx7
28252   { 12190,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12190 = V_CMPS_NLE_F32_e32_gfx6_gfx7
28254   { 12192,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12192 = V_CMPS_NLE_F64_e32_gfx6_gfx7
28256   { 12194,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12194 = V_CMPS_NLG_F32_e32_gfx6_gfx7
28258   { 12196,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12196 = V_CMPS_NLG_F64_e32_gfx6_gfx7
28260   { 12198,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12198 = V_CMPS_NLT_F32_e32_gfx6_gfx7
28262   { 12200,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12200 = V_CMPS_NLT_F64_e32_gfx6_gfx7
28264   { 12202,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12202 = V_CMPS_O_F32_e32_gfx6_gfx7
28266   { 12204,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12204 = V_CMPS_O_F64_e32_gfx6_gfx7
28268   { 12206,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12206 = V_CMPS_TRU_F32_e32_gfx6_gfx7
28270   { 12208,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12208 = V_CMPS_TRU_F64_e32_gfx6_gfx7
28272   { 12210,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12210 = V_CMPS_U_F32_e32_gfx6_gfx7
28274   { 12212,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12212 = V_CMPS_U_F64_e32_gfx6_gfx7
28990   { 12928,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #12928 = V_CMP_CLASS_F16_e32_gfx10
28991   { 12929,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #12929 = V_CMP_CLASS_F16_e32_vi
28994   { 12932,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #12932 = V_CMP_CLASS_F16_sdwa_gfx10
28995   { 12933,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #12933 = V_CMP_CLASS_F16_sdwa_gfx9
28996   { 12934,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #12934 = V_CMP_CLASS_F16_sdwa_vi
28997   { 12935,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12935 = V_CMP_CLASS_F32_e32_gfx10
28998   { 12936,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12936 = V_CMP_CLASS_F32_e32_gfx6_gfx7
28999   { 12937,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12937 = V_CMP_CLASS_F32_e32_vi
29003   { 12941,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #12941 = V_CMP_CLASS_F32_sdwa_gfx10
29004   { 12942,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #12942 = V_CMP_CLASS_F32_sdwa_gfx9
29005   { 12943,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #12943 = V_CMP_CLASS_F32_sdwa_vi
29006   { 12944,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo325, -1 ,nullptr },  // Inst #12944 = V_CMP_CLASS_F64_e32_gfx10
29007   { 12945,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo325, -1 ,nullptr },  // Inst #12945 = V_CMP_CLASS_F64_e32_gfx6_gfx7
29008   { 12946,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo325, -1 ,nullptr },  // Inst #12946 = V_CMP_CLASS_F64_e32_vi
29012   { 12950,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #12950 = V_CMP_EQ_F16_e32_gfx10
29013   { 12951,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #12951 = V_CMP_EQ_F16_e32_vi
29016   { 12954,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #12954 = V_CMP_EQ_F16_sdwa_gfx10
29017   { 12955,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #12955 = V_CMP_EQ_F16_sdwa_gfx9
29018   { 12956,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #12956 = V_CMP_EQ_F16_sdwa_vi
29019   { 12957,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12957 = V_CMP_EQ_F32_e32_gfx10
29020   { 12958,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12958 = V_CMP_EQ_F32_e32_gfx6_gfx7
29021   { 12959,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #12959 = V_CMP_EQ_F32_e32_vi
29025   { 12963,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #12963 = V_CMP_EQ_F32_sdwa_gfx10
29026   { 12964,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #12964 = V_CMP_EQ_F32_sdwa_gfx9
29027   { 12965,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #12965 = V_CMP_EQ_F32_sdwa_vi
29028   { 12966,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12966 = V_CMP_EQ_F64_e32_gfx10
29029   { 12967,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12967 = V_CMP_EQ_F64_e32_gfx6_gfx7
29030   { 12968,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #12968 = V_CMP_EQ_F64_e32_vi
29034   { 12972,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #12972 = V_CMP_EQ_I16_e32_gfx10
29035   { 12973,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #12973 = V_CMP_EQ_I16_e32_vi
29038   { 12976,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #12976 = V_CMP_EQ_I16_sdwa_gfx10
29039   { 12977,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #12977 = V_CMP_EQ_I16_sdwa_gfx9
29040   { 12978,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #12978 = V_CMP_EQ_I16_sdwa_vi
29041   { 12979,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #12979 = V_CMP_EQ_I32_e32_gfx10
29042   { 12980,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #12980 = V_CMP_EQ_I32_e32_gfx6_gfx7
29043   { 12981,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #12981 = V_CMP_EQ_I32_e32_vi
29047   { 12985,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #12985 = V_CMP_EQ_I32_sdwa_gfx10
29048   { 12986,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #12986 = V_CMP_EQ_I32_sdwa_gfx9
29049   { 12987,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #12987 = V_CMP_EQ_I32_sdwa_vi
29050   { 12988,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #12988 = V_CMP_EQ_I64_e32_gfx10
29051   { 12989,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #12989 = V_CMP_EQ_I64_e32_gfx6_gfx7
29052   { 12990,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #12990 = V_CMP_EQ_I64_e32_vi
29056   { 12994,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #12994 = V_CMP_EQ_U16_e32_gfx10
29057   { 12995,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #12995 = V_CMP_EQ_U16_e32_vi
29060   { 12998,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #12998 = V_CMP_EQ_U16_sdwa_gfx10
29061   { 12999,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #12999 = V_CMP_EQ_U16_sdwa_gfx9
29062   { 13000,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13000 = V_CMP_EQ_U16_sdwa_vi
29063   { 13001,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13001 = V_CMP_EQ_U32_e32_gfx10
29064   { 13002,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13002 = V_CMP_EQ_U32_e32_gfx6_gfx7
29065   { 13003,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13003 = V_CMP_EQ_U32_e32_vi
29069   { 13007,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13007 = V_CMP_EQ_U32_sdwa_gfx10
29070   { 13008,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13008 = V_CMP_EQ_U32_sdwa_gfx9
29071   { 13009,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13009 = V_CMP_EQ_U32_sdwa_vi
29072   { 13010,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13010 = V_CMP_EQ_U64_e32_gfx10
29073   { 13011,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13011 = V_CMP_EQ_U64_e32_gfx6_gfx7
29074   { 13012,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13012 = V_CMP_EQ_U64_e32_vi
29078   { 13016,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13016 = V_CMP_F_F16_e32_gfx10
29079   { 13017,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13017 = V_CMP_F_F16_e32_vi
29082   { 13020,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13020 = V_CMP_F_F16_sdwa_gfx10
29083   { 13021,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13021 = V_CMP_F_F16_sdwa_gfx9
29084   { 13022,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13022 = V_CMP_F_F16_sdwa_vi
29085   { 13023,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13023 = V_CMP_F_F32_e32_gfx10
29086   { 13024,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13024 = V_CMP_F_F32_e32_gfx6_gfx7
29087   { 13025,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13025 = V_CMP_F_F32_e32_vi
29091   { 13029,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13029 = V_CMP_F_F32_sdwa_gfx10
29092   { 13030,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13030 = V_CMP_F_F32_sdwa_gfx9
29093   { 13031,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13031 = V_CMP_F_F32_sdwa_vi
29094   { 13032,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13032 = V_CMP_F_F64_e32_gfx10
29095   { 13033,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13033 = V_CMP_F_F64_e32_gfx6_gfx7
29096   { 13034,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13034 = V_CMP_F_F64_e32_vi
29100   { 13038,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13038 = V_CMP_F_I16_e32_vi
29102   { 13040,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13040 = V_CMP_F_I16_sdwa_gfx9
29103   { 13041,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13041 = V_CMP_F_I16_sdwa_vi
29104   { 13042,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13042 = V_CMP_F_I32_e32_gfx10
29105   { 13043,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13043 = V_CMP_F_I32_e32_gfx6_gfx7
29106   { 13044,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13044 = V_CMP_F_I32_e32_vi
29110   { 13048,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13048 = V_CMP_F_I32_sdwa_gfx10
29111   { 13049,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13049 = V_CMP_F_I32_sdwa_gfx9
29112   { 13050,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13050 = V_CMP_F_I32_sdwa_vi
29113   { 13051,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13051 = V_CMP_F_I64_e32_gfx10
29114   { 13052,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13052 = V_CMP_F_I64_e32_gfx6_gfx7
29115   { 13053,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13053 = V_CMP_F_I64_e32_vi
29119   { 13057,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13057 = V_CMP_F_U16_e32_vi
29121   { 13059,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13059 = V_CMP_F_U16_sdwa_gfx9
29122   { 13060,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13060 = V_CMP_F_U16_sdwa_vi
29123   { 13061,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13061 = V_CMP_F_U32_e32_gfx10
29124   { 13062,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13062 = V_CMP_F_U32_e32_gfx6_gfx7
29125   { 13063,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13063 = V_CMP_F_U32_e32_vi
29129   { 13067,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13067 = V_CMP_F_U32_sdwa_gfx10
29130   { 13068,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13068 = V_CMP_F_U32_sdwa_gfx9
29131   { 13069,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13069 = V_CMP_F_U32_sdwa_vi
29132   { 13070,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13070 = V_CMP_F_U64_e32_gfx10
29133   { 13071,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13071 = V_CMP_F_U64_e32_gfx6_gfx7
29134   { 13072,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13072 = V_CMP_F_U64_e32_vi
29138   { 13076,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13076 = V_CMP_GE_F16_e32_gfx10
29139   { 13077,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13077 = V_CMP_GE_F16_e32_vi
29142   { 13080,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13080 = V_CMP_GE_F16_sdwa_gfx10
29143   { 13081,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13081 = V_CMP_GE_F16_sdwa_gfx9
29144   { 13082,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13082 = V_CMP_GE_F16_sdwa_vi
29145   { 13083,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13083 = V_CMP_GE_F32_e32_gfx10
29146   { 13084,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13084 = V_CMP_GE_F32_e32_gfx6_gfx7
29147   { 13085,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13085 = V_CMP_GE_F32_e32_vi
29151   { 13089,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13089 = V_CMP_GE_F32_sdwa_gfx10
29152   { 13090,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13090 = V_CMP_GE_F32_sdwa_gfx9
29153   { 13091,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13091 = V_CMP_GE_F32_sdwa_vi
29154   { 13092,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13092 = V_CMP_GE_F64_e32_gfx10
29155   { 13093,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13093 = V_CMP_GE_F64_e32_gfx6_gfx7
29156   { 13094,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13094 = V_CMP_GE_F64_e32_vi
29160   { 13098,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13098 = V_CMP_GE_I16_e32_gfx10
29161   { 13099,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13099 = V_CMP_GE_I16_e32_vi
29164   { 13102,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13102 = V_CMP_GE_I16_sdwa_gfx10
29165   { 13103,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13103 = V_CMP_GE_I16_sdwa_gfx9
29166   { 13104,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13104 = V_CMP_GE_I16_sdwa_vi
29167   { 13105,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13105 = V_CMP_GE_I32_e32_gfx10
29168   { 13106,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13106 = V_CMP_GE_I32_e32_gfx6_gfx7
29169   { 13107,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13107 = V_CMP_GE_I32_e32_vi
29173   { 13111,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13111 = V_CMP_GE_I32_sdwa_gfx10
29174   { 13112,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13112 = V_CMP_GE_I32_sdwa_gfx9
29175   { 13113,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13113 = V_CMP_GE_I32_sdwa_vi
29176   { 13114,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13114 = V_CMP_GE_I64_e32_gfx10
29177   { 13115,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13115 = V_CMP_GE_I64_e32_gfx6_gfx7
29178   { 13116,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13116 = V_CMP_GE_I64_e32_vi
29182   { 13120,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13120 = V_CMP_GE_U16_e32_gfx10
29183   { 13121,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13121 = V_CMP_GE_U16_e32_vi
29186   { 13124,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13124 = V_CMP_GE_U16_sdwa_gfx10
29187   { 13125,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13125 = V_CMP_GE_U16_sdwa_gfx9
29188   { 13126,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13126 = V_CMP_GE_U16_sdwa_vi
29189   { 13127,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13127 = V_CMP_GE_U32_e32_gfx10
29190   { 13128,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13128 = V_CMP_GE_U32_e32_gfx6_gfx7
29191   { 13129,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13129 = V_CMP_GE_U32_e32_vi
29195   { 13133,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13133 = V_CMP_GE_U32_sdwa_gfx10
29196   { 13134,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13134 = V_CMP_GE_U32_sdwa_gfx9
29197   { 13135,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13135 = V_CMP_GE_U32_sdwa_vi
29198   { 13136,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13136 = V_CMP_GE_U64_e32_gfx10
29199   { 13137,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13137 = V_CMP_GE_U64_e32_gfx6_gfx7
29200   { 13138,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13138 = V_CMP_GE_U64_e32_vi
29204   { 13142,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13142 = V_CMP_GT_F16_e32_gfx10
29205   { 13143,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13143 = V_CMP_GT_F16_e32_vi
29208   { 13146,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13146 = V_CMP_GT_F16_sdwa_gfx10
29209   { 13147,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13147 = V_CMP_GT_F16_sdwa_gfx9
29210   { 13148,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13148 = V_CMP_GT_F16_sdwa_vi
29211   { 13149,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13149 = V_CMP_GT_F32_e32_gfx10
29212   { 13150,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13150 = V_CMP_GT_F32_e32_gfx6_gfx7
29213   { 13151,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13151 = V_CMP_GT_F32_e32_vi
29217   { 13155,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13155 = V_CMP_GT_F32_sdwa_gfx10
29218   { 13156,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13156 = V_CMP_GT_F32_sdwa_gfx9
29219   { 13157,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13157 = V_CMP_GT_F32_sdwa_vi
29220   { 13158,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13158 = V_CMP_GT_F64_e32_gfx10
29221   { 13159,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13159 = V_CMP_GT_F64_e32_gfx6_gfx7
29222   { 13160,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13160 = V_CMP_GT_F64_e32_vi
29226   { 13164,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13164 = V_CMP_GT_I16_e32_gfx10
29227   { 13165,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13165 = V_CMP_GT_I16_e32_vi
29230   { 13168,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13168 = V_CMP_GT_I16_sdwa_gfx10
29231   { 13169,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13169 = V_CMP_GT_I16_sdwa_gfx9
29232   { 13170,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13170 = V_CMP_GT_I16_sdwa_vi
29233   { 13171,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13171 = V_CMP_GT_I32_e32_gfx10
29234   { 13172,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13172 = V_CMP_GT_I32_e32_gfx6_gfx7
29235   { 13173,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13173 = V_CMP_GT_I32_e32_vi
29239   { 13177,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13177 = V_CMP_GT_I32_sdwa_gfx10
29240   { 13178,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13178 = V_CMP_GT_I32_sdwa_gfx9
29241   { 13179,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13179 = V_CMP_GT_I32_sdwa_vi
29242   { 13180,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13180 = V_CMP_GT_I64_e32_gfx10
29243   { 13181,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13181 = V_CMP_GT_I64_e32_gfx6_gfx7
29244   { 13182,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13182 = V_CMP_GT_I64_e32_vi
29248   { 13186,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13186 = V_CMP_GT_U16_e32_gfx10
29249   { 13187,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13187 = V_CMP_GT_U16_e32_vi
29252   { 13190,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13190 = V_CMP_GT_U16_sdwa_gfx10
29253   { 13191,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13191 = V_CMP_GT_U16_sdwa_gfx9
29254   { 13192,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13192 = V_CMP_GT_U16_sdwa_vi
29255   { 13193,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13193 = V_CMP_GT_U32_e32_gfx10
29256   { 13194,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13194 = V_CMP_GT_U32_e32_gfx6_gfx7
29257   { 13195,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13195 = V_CMP_GT_U32_e32_vi
29261   { 13199,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13199 = V_CMP_GT_U32_sdwa_gfx10
29262   { 13200,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13200 = V_CMP_GT_U32_sdwa_gfx9
29263   { 13201,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13201 = V_CMP_GT_U32_sdwa_vi
29264   { 13202,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13202 = V_CMP_GT_U64_e32_gfx10
29265   { 13203,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13203 = V_CMP_GT_U64_e32_gfx6_gfx7
29266   { 13204,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13204 = V_CMP_GT_U64_e32_vi
29270   { 13208,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13208 = V_CMP_LE_F16_e32_gfx10
29271   { 13209,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13209 = V_CMP_LE_F16_e32_vi
29274   { 13212,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13212 = V_CMP_LE_F16_sdwa_gfx10
29275   { 13213,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13213 = V_CMP_LE_F16_sdwa_gfx9
29276   { 13214,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13214 = V_CMP_LE_F16_sdwa_vi
29277   { 13215,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13215 = V_CMP_LE_F32_e32_gfx10
29278   { 13216,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13216 = V_CMP_LE_F32_e32_gfx6_gfx7
29279   { 13217,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13217 = V_CMP_LE_F32_e32_vi
29283   { 13221,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13221 = V_CMP_LE_F32_sdwa_gfx10
29284   { 13222,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13222 = V_CMP_LE_F32_sdwa_gfx9
29285   { 13223,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13223 = V_CMP_LE_F32_sdwa_vi
29286   { 13224,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13224 = V_CMP_LE_F64_e32_gfx10
29287   { 13225,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13225 = V_CMP_LE_F64_e32_gfx6_gfx7
29288   { 13226,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13226 = V_CMP_LE_F64_e32_vi
29292   { 13230,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13230 = V_CMP_LE_I16_e32_gfx10
29293   { 13231,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13231 = V_CMP_LE_I16_e32_vi
29296   { 13234,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13234 = V_CMP_LE_I16_sdwa_gfx10
29297   { 13235,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13235 = V_CMP_LE_I16_sdwa_gfx9
29298   { 13236,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13236 = V_CMP_LE_I16_sdwa_vi
29299   { 13237,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13237 = V_CMP_LE_I32_e32_gfx10
29300   { 13238,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13238 = V_CMP_LE_I32_e32_gfx6_gfx7
29301   { 13239,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13239 = V_CMP_LE_I32_e32_vi
29305   { 13243,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13243 = V_CMP_LE_I32_sdwa_gfx10
29306   { 13244,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13244 = V_CMP_LE_I32_sdwa_gfx9
29307   { 13245,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13245 = V_CMP_LE_I32_sdwa_vi
29308   { 13246,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13246 = V_CMP_LE_I64_e32_gfx10
29309   { 13247,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13247 = V_CMP_LE_I64_e32_gfx6_gfx7
29310   { 13248,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13248 = V_CMP_LE_I64_e32_vi
29314   { 13252,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13252 = V_CMP_LE_U16_e32_gfx10
29315   { 13253,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13253 = V_CMP_LE_U16_e32_vi
29318   { 13256,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13256 = V_CMP_LE_U16_sdwa_gfx10
29319   { 13257,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13257 = V_CMP_LE_U16_sdwa_gfx9
29320   { 13258,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13258 = V_CMP_LE_U16_sdwa_vi
29321   { 13259,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13259 = V_CMP_LE_U32_e32_gfx10
29322   { 13260,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13260 = V_CMP_LE_U32_e32_gfx6_gfx7
29323   { 13261,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13261 = V_CMP_LE_U32_e32_vi
29327   { 13265,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13265 = V_CMP_LE_U32_sdwa_gfx10
29328   { 13266,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13266 = V_CMP_LE_U32_sdwa_gfx9
29329   { 13267,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13267 = V_CMP_LE_U32_sdwa_vi
29330   { 13268,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13268 = V_CMP_LE_U64_e32_gfx10
29331   { 13269,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13269 = V_CMP_LE_U64_e32_gfx6_gfx7
29332   { 13270,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13270 = V_CMP_LE_U64_e32_vi
29336   { 13274,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13274 = V_CMP_LG_F16_e32_gfx10
29337   { 13275,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13275 = V_CMP_LG_F16_e32_vi
29340   { 13278,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13278 = V_CMP_LG_F16_sdwa_gfx10
29341   { 13279,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13279 = V_CMP_LG_F16_sdwa_gfx9
29342   { 13280,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13280 = V_CMP_LG_F16_sdwa_vi
29343   { 13281,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13281 = V_CMP_LG_F32_e32_gfx10
29344   { 13282,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13282 = V_CMP_LG_F32_e32_gfx6_gfx7
29345   { 13283,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13283 = V_CMP_LG_F32_e32_vi
29349   { 13287,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13287 = V_CMP_LG_F32_sdwa_gfx10
29350   { 13288,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13288 = V_CMP_LG_F32_sdwa_gfx9
29351   { 13289,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13289 = V_CMP_LG_F32_sdwa_vi
29352   { 13290,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13290 = V_CMP_LG_F64_e32_gfx10
29353   { 13291,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13291 = V_CMP_LG_F64_e32_gfx6_gfx7
29354   { 13292,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13292 = V_CMP_LG_F64_e32_vi
29358   { 13296,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13296 = V_CMP_LT_F16_e32_gfx10
29359   { 13297,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13297 = V_CMP_LT_F16_e32_vi
29362   { 13300,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13300 = V_CMP_LT_F16_sdwa_gfx10
29363   { 13301,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13301 = V_CMP_LT_F16_sdwa_gfx9
29364   { 13302,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13302 = V_CMP_LT_F16_sdwa_vi
29365   { 13303,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13303 = V_CMP_LT_F32_e32_gfx10
29366   { 13304,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13304 = V_CMP_LT_F32_e32_gfx6_gfx7
29367   { 13305,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13305 = V_CMP_LT_F32_e32_vi
29371   { 13309,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13309 = V_CMP_LT_F32_sdwa_gfx10
29372   { 13310,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13310 = V_CMP_LT_F32_sdwa_gfx9
29373   { 13311,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13311 = V_CMP_LT_F32_sdwa_vi
29374   { 13312,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13312 = V_CMP_LT_F64_e32_gfx10
29375   { 13313,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13313 = V_CMP_LT_F64_e32_gfx6_gfx7
29376   { 13314,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13314 = V_CMP_LT_F64_e32_vi
29380   { 13318,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13318 = V_CMP_LT_I16_e32_gfx10
29381   { 13319,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13319 = V_CMP_LT_I16_e32_vi
29384   { 13322,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13322 = V_CMP_LT_I16_sdwa_gfx10
29385   { 13323,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13323 = V_CMP_LT_I16_sdwa_gfx9
29386   { 13324,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13324 = V_CMP_LT_I16_sdwa_vi
29387   { 13325,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13325 = V_CMP_LT_I32_e32_gfx10
29388   { 13326,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13326 = V_CMP_LT_I32_e32_gfx6_gfx7
29389   { 13327,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13327 = V_CMP_LT_I32_e32_vi
29393   { 13331,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13331 = V_CMP_LT_I32_sdwa_gfx10
29394   { 13332,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13332 = V_CMP_LT_I32_sdwa_gfx9
29395   { 13333,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13333 = V_CMP_LT_I32_sdwa_vi
29396   { 13334,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13334 = V_CMP_LT_I64_e32_gfx10
29397   { 13335,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13335 = V_CMP_LT_I64_e32_gfx6_gfx7
29398   { 13336,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13336 = V_CMP_LT_I64_e32_vi
29402   { 13340,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13340 = V_CMP_LT_U16_e32_gfx10
29403   { 13341,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13341 = V_CMP_LT_U16_e32_vi
29406   { 13344,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13344 = V_CMP_LT_U16_sdwa_gfx10
29407   { 13345,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13345 = V_CMP_LT_U16_sdwa_gfx9
29408   { 13346,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13346 = V_CMP_LT_U16_sdwa_vi
29409   { 13347,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13347 = V_CMP_LT_U32_e32_gfx10
29410   { 13348,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13348 = V_CMP_LT_U32_e32_gfx6_gfx7
29411   { 13349,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13349 = V_CMP_LT_U32_e32_vi
29415   { 13353,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13353 = V_CMP_LT_U32_sdwa_gfx10
29416   { 13354,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13354 = V_CMP_LT_U32_sdwa_gfx9
29417   { 13355,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13355 = V_CMP_LT_U32_sdwa_vi
29418   { 13356,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13356 = V_CMP_LT_U64_e32_gfx10
29419   { 13357,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13357 = V_CMP_LT_U64_e32_gfx6_gfx7
29420   { 13358,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13358 = V_CMP_LT_U64_e32_vi
29424   { 13362,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13362 = V_CMP_NEQ_F16_e32_gfx10
29425   { 13363,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13363 = V_CMP_NEQ_F16_e32_vi
29428   { 13366,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13366 = V_CMP_NEQ_F16_sdwa_gfx10
29429   { 13367,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13367 = V_CMP_NEQ_F16_sdwa_gfx9
29430   { 13368,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13368 = V_CMP_NEQ_F16_sdwa_vi
29431   { 13369,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13369 = V_CMP_NEQ_F32_e32_gfx10
29432   { 13370,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13370 = V_CMP_NEQ_F32_e32_gfx6_gfx7
29433   { 13371,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13371 = V_CMP_NEQ_F32_e32_vi
29437   { 13375,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13375 = V_CMP_NEQ_F32_sdwa_gfx10
29438   { 13376,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13376 = V_CMP_NEQ_F32_sdwa_gfx9
29439   { 13377,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13377 = V_CMP_NEQ_F32_sdwa_vi
29440   { 13378,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13378 = V_CMP_NEQ_F64_e32_gfx10
29441   { 13379,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13379 = V_CMP_NEQ_F64_e32_gfx6_gfx7
29442   { 13380,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13380 = V_CMP_NEQ_F64_e32_vi
29446   { 13384,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13384 = V_CMP_NE_I16_e32_gfx10
29447   { 13385,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13385 = V_CMP_NE_I16_e32_vi
29450   { 13388,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13388 = V_CMP_NE_I16_sdwa_gfx10
29451   { 13389,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13389 = V_CMP_NE_I16_sdwa_gfx9
29452   { 13390,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13390 = V_CMP_NE_I16_sdwa_vi
29453   { 13391,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13391 = V_CMP_NE_I32_e32_gfx10
29454   { 13392,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13392 = V_CMP_NE_I32_e32_gfx6_gfx7
29455   { 13393,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13393 = V_CMP_NE_I32_e32_vi
29459   { 13397,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13397 = V_CMP_NE_I32_sdwa_gfx10
29460   { 13398,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13398 = V_CMP_NE_I32_sdwa_gfx9
29461   { 13399,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13399 = V_CMP_NE_I32_sdwa_vi
29462   { 13400,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13400 = V_CMP_NE_I64_e32_gfx10
29463   { 13401,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13401 = V_CMP_NE_I64_e32_gfx6_gfx7
29464   { 13402,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13402 = V_CMP_NE_I64_e32_vi
29468   { 13406,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13406 = V_CMP_NE_U16_e32_gfx10
29469   { 13407,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13407 = V_CMP_NE_U16_e32_vi
29472   { 13410,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13410 = V_CMP_NE_U16_sdwa_gfx10
29473   { 13411,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13411 = V_CMP_NE_U16_sdwa_gfx9
29474   { 13412,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13412 = V_CMP_NE_U16_sdwa_vi
29475   { 13413,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13413 = V_CMP_NE_U32_e32_gfx10
29476   { 13414,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13414 = V_CMP_NE_U32_e32_gfx6_gfx7
29477   { 13415,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13415 = V_CMP_NE_U32_e32_vi
29481   { 13419,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13419 = V_CMP_NE_U32_sdwa_gfx10
29482   { 13420,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13420 = V_CMP_NE_U32_sdwa_gfx9
29483   { 13421,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13421 = V_CMP_NE_U32_sdwa_vi
29484   { 13422,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13422 = V_CMP_NE_U64_e32_gfx10
29485   { 13423,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13423 = V_CMP_NE_U64_e32_gfx6_gfx7
29486   { 13424,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13424 = V_CMP_NE_U64_e32_vi
29490   { 13428,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13428 = V_CMP_NGE_F16_e32_gfx10
29491   { 13429,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13429 = V_CMP_NGE_F16_e32_vi
29494   { 13432,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13432 = V_CMP_NGE_F16_sdwa_gfx10
29495   { 13433,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13433 = V_CMP_NGE_F16_sdwa_gfx9
29496   { 13434,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13434 = V_CMP_NGE_F16_sdwa_vi
29497   { 13435,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13435 = V_CMP_NGE_F32_e32_gfx10
29498   { 13436,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13436 = V_CMP_NGE_F32_e32_gfx6_gfx7
29499   { 13437,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13437 = V_CMP_NGE_F32_e32_vi
29503   { 13441,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13441 = V_CMP_NGE_F32_sdwa_gfx10
29504   { 13442,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13442 = V_CMP_NGE_F32_sdwa_gfx9
29505   { 13443,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13443 = V_CMP_NGE_F32_sdwa_vi
29506   { 13444,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13444 = V_CMP_NGE_F64_e32_gfx10
29507   { 13445,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13445 = V_CMP_NGE_F64_e32_gfx6_gfx7
29508   { 13446,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13446 = V_CMP_NGE_F64_e32_vi
29512   { 13450,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13450 = V_CMP_NGT_F16_e32_gfx10
29513   { 13451,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13451 = V_CMP_NGT_F16_e32_vi
29516   { 13454,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13454 = V_CMP_NGT_F16_sdwa_gfx10
29517   { 13455,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13455 = V_CMP_NGT_F16_sdwa_gfx9
29518   { 13456,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13456 = V_CMP_NGT_F16_sdwa_vi
29519   { 13457,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13457 = V_CMP_NGT_F32_e32_gfx10
29520   { 13458,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13458 = V_CMP_NGT_F32_e32_gfx6_gfx7
29521   { 13459,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13459 = V_CMP_NGT_F32_e32_vi
29525   { 13463,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13463 = V_CMP_NGT_F32_sdwa_gfx10
29526   { 13464,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13464 = V_CMP_NGT_F32_sdwa_gfx9
29527   { 13465,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13465 = V_CMP_NGT_F32_sdwa_vi
29528   { 13466,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13466 = V_CMP_NGT_F64_e32_gfx10
29529   { 13467,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13467 = V_CMP_NGT_F64_e32_gfx6_gfx7
29530   { 13468,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13468 = V_CMP_NGT_F64_e32_vi
29534   { 13472,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13472 = V_CMP_NLE_F16_e32_gfx10
29535   { 13473,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13473 = V_CMP_NLE_F16_e32_vi
29538   { 13476,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13476 = V_CMP_NLE_F16_sdwa_gfx10
29539   { 13477,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13477 = V_CMP_NLE_F16_sdwa_gfx9
29540   { 13478,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13478 = V_CMP_NLE_F16_sdwa_vi
29541   { 13479,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13479 = V_CMP_NLE_F32_e32_gfx10
29542   { 13480,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13480 = V_CMP_NLE_F32_e32_gfx6_gfx7
29543   { 13481,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13481 = V_CMP_NLE_F32_e32_vi
29547   { 13485,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13485 = V_CMP_NLE_F32_sdwa_gfx10
29548   { 13486,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13486 = V_CMP_NLE_F32_sdwa_gfx9
29549   { 13487,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13487 = V_CMP_NLE_F32_sdwa_vi
29550   { 13488,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13488 = V_CMP_NLE_F64_e32_gfx10
29551   { 13489,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13489 = V_CMP_NLE_F64_e32_gfx6_gfx7
29552   { 13490,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13490 = V_CMP_NLE_F64_e32_vi
29556   { 13494,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13494 = V_CMP_NLG_F16_e32_gfx10
29557   { 13495,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13495 = V_CMP_NLG_F16_e32_vi
29560   { 13498,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13498 = V_CMP_NLG_F16_sdwa_gfx10
29561   { 13499,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13499 = V_CMP_NLG_F16_sdwa_gfx9
29562   { 13500,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13500 = V_CMP_NLG_F16_sdwa_vi
29563   { 13501,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13501 = V_CMP_NLG_F32_e32_gfx10
29564   { 13502,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13502 = V_CMP_NLG_F32_e32_gfx6_gfx7
29565   { 13503,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13503 = V_CMP_NLG_F32_e32_vi
29569   { 13507,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13507 = V_CMP_NLG_F32_sdwa_gfx10
29570   { 13508,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13508 = V_CMP_NLG_F32_sdwa_gfx9
29571   { 13509,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13509 = V_CMP_NLG_F32_sdwa_vi
29572   { 13510,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13510 = V_CMP_NLG_F64_e32_gfx10
29573   { 13511,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13511 = V_CMP_NLG_F64_e32_gfx6_gfx7
29574   { 13512,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13512 = V_CMP_NLG_F64_e32_vi
29578   { 13516,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13516 = V_CMP_NLT_F16_e32_gfx10
29579   { 13517,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13517 = V_CMP_NLT_F16_e32_vi
29582   { 13520,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13520 = V_CMP_NLT_F16_sdwa_gfx10
29583   { 13521,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13521 = V_CMP_NLT_F16_sdwa_gfx9
29584   { 13522,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13522 = V_CMP_NLT_F16_sdwa_vi
29585   { 13523,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13523 = V_CMP_NLT_F32_e32_gfx10
29586   { 13524,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13524 = V_CMP_NLT_F32_e32_gfx6_gfx7
29587   { 13525,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13525 = V_CMP_NLT_F32_e32_vi
29591   { 13529,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13529 = V_CMP_NLT_F32_sdwa_gfx10
29592   { 13530,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13530 = V_CMP_NLT_F32_sdwa_gfx9
29593   { 13531,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13531 = V_CMP_NLT_F32_sdwa_vi
29594   { 13532,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13532 = V_CMP_NLT_F64_e32_gfx10
29595   { 13533,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13533 = V_CMP_NLT_F64_e32_gfx6_gfx7
29596   { 13534,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13534 = V_CMP_NLT_F64_e32_vi
29600   { 13538,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13538 = V_CMP_O_F16_e32_gfx10
29601   { 13539,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13539 = V_CMP_O_F16_e32_vi
29604   { 13542,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13542 = V_CMP_O_F16_sdwa_gfx10
29605   { 13543,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13543 = V_CMP_O_F16_sdwa_gfx9
29606   { 13544,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13544 = V_CMP_O_F16_sdwa_vi
29607   { 13545,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13545 = V_CMP_O_F32_e32_gfx10
29608   { 13546,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13546 = V_CMP_O_F32_e32_gfx6_gfx7
29609   { 13547,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13547 = V_CMP_O_F32_e32_vi
29613   { 13551,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13551 = V_CMP_O_F32_sdwa_gfx10
29614   { 13552,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13552 = V_CMP_O_F32_sdwa_gfx9
29615   { 13553,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13553 = V_CMP_O_F32_sdwa_vi
29616   { 13554,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13554 = V_CMP_O_F64_e32_gfx10
29617   { 13555,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13555 = V_CMP_O_F64_e32_gfx6_gfx7
29618   { 13556,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13556 = V_CMP_O_F64_e32_vi
29622   { 13560,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13560 = V_CMP_TRU_F16_e32_gfx10
29623   { 13561,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13561 = V_CMP_TRU_F16_e32_vi
29626   { 13564,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13564 = V_CMP_TRU_F16_sdwa_gfx10
29627   { 13565,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13565 = V_CMP_TRU_F16_sdwa_gfx9
29628   { 13566,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13566 = V_CMP_TRU_F16_sdwa_vi
29629   { 13567,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13567 = V_CMP_TRU_F32_e32_gfx10
29630   { 13568,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13568 = V_CMP_TRU_F32_e32_gfx6_gfx7
29631   { 13569,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13569 = V_CMP_TRU_F32_e32_vi
29635   { 13573,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13573 = V_CMP_TRU_F32_sdwa_gfx10
29636   { 13574,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13574 = V_CMP_TRU_F32_sdwa_gfx9
29637   { 13575,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13575 = V_CMP_TRU_F32_sdwa_vi
29638   { 13576,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13576 = V_CMP_TRU_F64_e32_gfx10
29639   { 13577,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13577 = V_CMP_TRU_F64_e32_gfx6_gfx7
29640   { 13578,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13578 = V_CMP_TRU_F64_e32_vi
29644   { 13582,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13582 = V_CMP_T_I16_e32_vi
29646   { 13584,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13584 = V_CMP_T_I16_sdwa_gfx9
29647   { 13585,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13585 = V_CMP_T_I16_sdwa_vi
29648   { 13586,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13586 = V_CMP_T_I32_e32_gfx10
29649   { 13587,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13587 = V_CMP_T_I32_e32_gfx6_gfx7
29650   { 13588,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13588 = V_CMP_T_I32_e32_vi
29654   { 13592,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13592 = V_CMP_T_I32_sdwa_gfx10
29655   { 13593,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13593 = V_CMP_T_I32_sdwa_gfx9
29656   { 13594,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13594 = V_CMP_T_I32_sdwa_vi
29657   { 13595,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13595 = V_CMP_T_I64_e32_gfx10
29658   { 13596,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13596 = V_CMP_T_I64_e32_gfx6_gfx7
29659   { 13597,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13597 = V_CMP_T_I64_e32_vi
29663   { 13601,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr },  // Inst #13601 = V_CMP_T_U16_e32_vi
29665   { 13603,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13603 = V_CMP_T_U16_sdwa_gfx9
29666   { 13604,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr },  // Inst #13604 = V_CMP_T_U16_sdwa_vi
29667   { 13605,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13605 = V_CMP_T_U32_e32_gfx10
29668   { 13606,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13606 = V_CMP_T_U32_e32_gfx6_gfx7
29669   { 13607,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr },  // Inst #13607 = V_CMP_T_U32_e32_vi
29673   { 13611,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13611 = V_CMP_T_U32_sdwa_gfx10
29674   { 13612,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13612 = V_CMP_T_U32_sdwa_gfx9
29675   { 13613,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr },  // Inst #13613 = V_CMP_T_U32_sdwa_vi
29676   { 13614,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13614 = V_CMP_T_U64_e32_gfx10
29677   { 13615,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13615 = V_CMP_T_U64_e32_gfx6_gfx7
29678   { 13616,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr },  // Inst #13616 = V_CMP_T_U64_e32_vi
29682   { 13620,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13620 = V_CMP_U_F16_e32_gfx10
29683   { 13621,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr },  // Inst #13621 = V_CMP_U_F16_e32_vi
29686   { 13624,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13624 = V_CMP_U_F16_sdwa_gfx10
29687   { 13625,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13625 = V_CMP_U_F16_sdwa_gfx9
29688   { 13626,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr },  // Inst #13626 = V_CMP_U_F16_sdwa_vi
29689   { 13627,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13627 = V_CMP_U_F32_e32_gfx10
29690   { 13628,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13628 = V_CMP_U_F32_e32_gfx6_gfx7
29691   { 13629,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr },  // Inst #13629 = V_CMP_U_F32_e32_vi
29695   { 13633,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13633 = V_CMP_U_F32_sdwa_gfx10
29696   { 13634,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13634 = V_CMP_U_F32_sdwa_gfx9
29697   { 13635,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr },  // Inst #13635 = V_CMP_U_F32_sdwa_vi
29698   { 13636,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13636 = V_CMP_U_F64_e32_gfx10
29699   { 13637,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13637 = V_CMP_U_F64_e32_gfx6_gfx7
29700   { 13638,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr },  // Inst #13638 = V_CMP_U_F64_e32_vi
31122   { 15060,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15060 = V_SUBBREV_CO_U32_dpp_gfx9
31123   { 15061,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15061 = V_SUBBREV_CO_U32_e32_gfx9
31125   { 15063,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15063 = V_SUBBREV_CO_U32_sdwa_gfx9
31126   { 15064,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15064 = V_SUBBREV_U32_dpp_vi
31127   { 15065,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15065 = V_SUBBREV_U32_e32_gfx6_gfx7
31128   { 15066,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15066 = V_SUBBREV_U32_e32_vi
31131   { 15069,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15069 = V_SUBBREV_U32_sdwa_vi
31132   { 15070,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15070 = V_SUBB_CO_U32_dpp_gfx9
31133   { 15071,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15071 = V_SUBB_CO_U32_e32_gfx9
31135   { 15073,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15073 = V_SUBB_CO_U32_sdwa_gfx9
31136   { 15074,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15074 = V_SUBB_U32_dpp_vi
31137   { 15075,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15075 = V_SUBB_U32_e32_gfx6_gfx7
31138   { 15076,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15076 = V_SUBB_U32_e32_vi
31141   { 15079,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15079 = V_SUBB_U32_sdwa_vi
31142   { 15080,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15080 = V_SUBREV_CO_CI_U32_dpp8_gfx10
31143   { 15081,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15081 = V_SUBREV_CO_CI_U32_dpp8_w32_gfx10
31144   { 15082,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15082 = V_SUBREV_CO_CI_U32_dpp8_w64_gfx10
31145   { 15083,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15083 = V_SUBREV_CO_CI_U32_dpp_gfx10
31146   { 15084,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15084 = V_SUBREV_CO_CI_U32_dpp_w32_gfx10
31147   { 15085,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15085 = V_SUBREV_CO_CI_U32_dpp_w64_gfx10
31148   { 15086,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15086 = V_SUBREV_CO_CI_U32_e32_gfx10
31150   { 15088,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15088 = V_SUBREV_CO_CI_U32_sdwa_gfx10
31151   { 15089,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15089 = V_SUBREV_CO_CI_U32_sdwa_w32_gfx10
31152   { 15090,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15090 = V_SUBREV_CO_CI_U32_sdwa_w64_gfx10
31153   { 15091,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15091 = V_SUBREV_CO_U32_dpp_gfx9
31154   { 15092,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15092 = V_SUBREV_CO_U32_e32_gfx9
31157   { 15095,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15095 = V_SUBREV_CO_U32_sdwa_gfx9
31180   { 15118,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15118 = V_SUBREV_I32_e32_gfx6_gfx7
31193   { 15131,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15131 = V_SUBREV_U32_dpp_vi
31195   { 15133,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15133 = V_SUBREV_U32_e32_vi
31199   { 15137,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15137 = V_SUBREV_U32_sdwa_vi
31200   { 15138,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15138 = V_SUB_CO_CI_U32_dpp8_gfx10
31201   { 15139,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15139 = V_SUB_CO_CI_U32_dpp8_w32_gfx10
31202   { 15140,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15140 = V_SUB_CO_CI_U32_dpp8_w64_gfx10
31203   { 15141,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15141 = V_SUB_CO_CI_U32_dpp_gfx10
31204   { 15142,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15142 = V_SUB_CO_CI_U32_dpp_w32_gfx10
31205   { 15143,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15143 = V_SUB_CO_CI_U32_dpp_w64_gfx10
31206   { 15144,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15144 = V_SUB_CO_CI_U32_e32_gfx10
31208   { 15146,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15146 = V_SUB_CO_CI_U32_sdwa_gfx10
31209   { 15147,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15147 = V_SUB_CO_CI_U32_sdwa_w32_gfx10
31210   { 15148,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15148 = V_SUB_CO_CI_U32_sdwa_w64_gfx10
31211   { 15149,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15149 = V_SUB_CO_U32_dpp_gfx9
31212   { 15150,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15150 = V_SUB_CO_U32_e32_gfx9
31215   { 15153,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15153 = V_SUB_CO_U32_sdwa_gfx9
31239   { 15177,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15177 = V_SUB_I32_e32_gfx6_gfx7
31256   { 15194,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15194 = V_SUB_U32_dpp_vi
31258   { 15196,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15196 = V_SUB_U32_e32_vi
31262   { 15200,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15200 = V_SUB_U32_sdwa_vi