reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

18382   { 2320,	8,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #2320 = V_ADDC_U32_dpp
18383   { 2321,	3,	1,	4,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #2321 = V_ADDC_U32_e32
18385   { 2323,	10,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #2323 = V_ADDC_U32_sdwa
18454   { 2392,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2392 = V_CMPSX_EQ_F32_e32
18459   { 2397,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2397 = V_CMPSX_EQ_F32_sdwa
18460   { 2398,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2398 = V_CMPSX_EQ_F64_e32
18464   { 2402,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2402 = V_CMPSX_F_F32_e32
18469   { 2407,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2407 = V_CMPSX_F_F32_sdwa
18470   { 2408,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2408 = V_CMPSX_F_F64_e32
18474   { 2412,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2412 = V_CMPSX_GE_F32_e32
18479   { 2417,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2417 = V_CMPSX_GE_F32_sdwa
18480   { 2418,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2418 = V_CMPSX_GE_F64_e32
18484   { 2422,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2422 = V_CMPSX_GT_F32_e32
18489   { 2427,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2427 = V_CMPSX_GT_F32_sdwa
18490   { 2428,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2428 = V_CMPSX_GT_F64_e32
18494   { 2432,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2432 = V_CMPSX_LE_F32_e32
18499   { 2437,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2437 = V_CMPSX_LE_F32_sdwa
18500   { 2438,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2438 = V_CMPSX_LE_F64_e32
18504   { 2442,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2442 = V_CMPSX_LG_F32_e32
18509   { 2447,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2447 = V_CMPSX_LG_F32_sdwa
18510   { 2448,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2448 = V_CMPSX_LG_F64_e32
18514   { 2452,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2452 = V_CMPSX_LT_F32_e32
18519   { 2457,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2457 = V_CMPSX_LT_F32_sdwa
18520   { 2458,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2458 = V_CMPSX_LT_F64_e32
18524   { 2462,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2462 = V_CMPSX_NEQ_F32_e32
18529   { 2467,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2467 = V_CMPSX_NEQ_F32_sdwa
18530   { 2468,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2468 = V_CMPSX_NEQ_F64_e32
18534   { 2472,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2472 = V_CMPSX_NGE_F32_e32
18539   { 2477,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2477 = V_CMPSX_NGE_F32_sdwa
18540   { 2478,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2478 = V_CMPSX_NGE_F64_e32
18544   { 2482,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2482 = V_CMPSX_NGT_F32_e32
18549   { 2487,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2487 = V_CMPSX_NGT_F32_sdwa
18550   { 2488,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2488 = V_CMPSX_NGT_F64_e32
18554   { 2492,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2492 = V_CMPSX_NLE_F32_e32
18559   { 2497,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2497 = V_CMPSX_NLE_F32_sdwa
18560   { 2498,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2498 = V_CMPSX_NLE_F64_e32
18564   { 2502,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2502 = V_CMPSX_NLG_F32_e32
18569   { 2507,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2507 = V_CMPSX_NLG_F32_sdwa
18570   { 2508,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2508 = V_CMPSX_NLG_F64_e32
18574   { 2512,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2512 = V_CMPSX_NLT_F32_e32
18579   { 2517,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2517 = V_CMPSX_NLT_F32_sdwa
18580   { 2518,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2518 = V_CMPSX_NLT_F64_e32
18584   { 2522,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2522 = V_CMPSX_O_F32_e32
18589   { 2527,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2527 = V_CMPSX_O_F32_sdwa
18590   { 2528,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2528 = V_CMPSX_O_F64_e32
18594   { 2532,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2532 = V_CMPSX_TRU_F32_e32
18599   { 2537,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2537 = V_CMPSX_TRU_F32_sdwa
18600   { 2538,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2538 = V_CMPSX_TRU_F64_e32
18604   { 2542,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2542 = V_CMPSX_U_F32_e32
18609   { 2547,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2547 = V_CMPSX_U_F32_sdwa
18610   { 2548,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2548 = V_CMPSX_U_F64_e32
18694   { 2632,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #2632 = V_CMPX_CLASS_F16_e32
18699   { 2637,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #2637 = V_CMPX_CLASS_F16_sdwa
18700   { 2638,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2638 = V_CMPX_CLASS_F32_e32
18705   { 2643,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2643 = V_CMPX_CLASS_F32_sdwa
18706   { 2644,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo325, -1 ,nullptr },  // Inst #2644 = V_CMPX_CLASS_F64_e32
18710   { 2648,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #2648 = V_CMPX_EQ_F16_e32
18715   { 2653,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #2653 = V_CMPX_EQ_F16_sdwa
18716   { 2654,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2654 = V_CMPX_EQ_F32_e32
18721   { 2659,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2659 = V_CMPX_EQ_F32_sdwa
18722   { 2660,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2660 = V_CMPX_EQ_F64_e32
18726   { 2664,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2664 = V_CMPX_EQ_I16_e32
18731   { 2669,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2669 = V_CMPX_EQ_I16_sdwa
18732   { 2670,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2670 = V_CMPX_EQ_I32_e32
18737   { 2675,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2675 = V_CMPX_EQ_I32_sdwa
18738   { 2676,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2676 = V_CMPX_EQ_I64_e32
18742   { 2680,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2680 = V_CMPX_EQ_U16_e32
18747   { 2685,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2685 = V_CMPX_EQ_U16_sdwa
18748   { 2686,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2686 = V_CMPX_EQ_U32_e32
18753   { 2691,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2691 = V_CMPX_EQ_U32_sdwa
18754   { 2692,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2692 = V_CMPX_EQ_U64_e32
18758   { 2696,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #2696 = V_CMPX_F_F16_e32
18763   { 2701,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #2701 = V_CMPX_F_F16_sdwa
18764   { 2702,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2702 = V_CMPX_F_F32_e32
18769   { 2707,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2707 = V_CMPX_F_F32_sdwa
18770   { 2708,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2708 = V_CMPX_F_F64_e32
18774   { 2712,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2712 = V_CMPX_F_I16_e32
18779   { 2717,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2717 = V_CMPX_F_I16_sdwa
18780   { 2718,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2718 = V_CMPX_F_I32_e32
18785   { 2723,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2723 = V_CMPX_F_I32_sdwa
18786   { 2724,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2724 = V_CMPX_F_I64_e32
18790   { 2728,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2728 = V_CMPX_F_U16_e32
18795   { 2733,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2733 = V_CMPX_F_U16_sdwa
18796   { 2734,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2734 = V_CMPX_F_U32_e32
18801   { 2739,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2739 = V_CMPX_F_U32_sdwa
18802   { 2740,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2740 = V_CMPX_F_U64_e32
18806   { 2744,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #2744 = V_CMPX_GE_F16_e32
18811   { 2749,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #2749 = V_CMPX_GE_F16_sdwa
18812   { 2750,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2750 = V_CMPX_GE_F32_e32
18817   { 2755,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2755 = V_CMPX_GE_F32_sdwa
18818   { 2756,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2756 = V_CMPX_GE_F64_e32
18822   { 2760,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2760 = V_CMPX_GE_I16_e32
18827   { 2765,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2765 = V_CMPX_GE_I16_sdwa
18828   { 2766,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2766 = V_CMPX_GE_I32_e32
18833   { 2771,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2771 = V_CMPX_GE_I32_sdwa
18834   { 2772,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2772 = V_CMPX_GE_I64_e32
18838   { 2776,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2776 = V_CMPX_GE_U16_e32
18843   { 2781,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2781 = V_CMPX_GE_U16_sdwa
18844   { 2782,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2782 = V_CMPX_GE_U32_e32
18849   { 2787,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2787 = V_CMPX_GE_U32_sdwa
18850   { 2788,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2788 = V_CMPX_GE_U64_e32
18854   { 2792,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #2792 = V_CMPX_GT_F16_e32
18859   { 2797,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #2797 = V_CMPX_GT_F16_sdwa
18860   { 2798,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2798 = V_CMPX_GT_F32_e32
18865   { 2803,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2803 = V_CMPX_GT_F32_sdwa
18866   { 2804,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2804 = V_CMPX_GT_F64_e32
18870   { 2808,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2808 = V_CMPX_GT_I16_e32
18875   { 2813,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2813 = V_CMPX_GT_I16_sdwa
18876   { 2814,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2814 = V_CMPX_GT_I32_e32
18881   { 2819,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2819 = V_CMPX_GT_I32_sdwa
18882   { 2820,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2820 = V_CMPX_GT_I64_e32
18886   { 2824,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2824 = V_CMPX_GT_U16_e32
18891   { 2829,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2829 = V_CMPX_GT_U16_sdwa
18892   { 2830,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2830 = V_CMPX_GT_U32_e32
18897   { 2835,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2835 = V_CMPX_GT_U32_sdwa
18898   { 2836,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2836 = V_CMPX_GT_U64_e32
18902   { 2840,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #2840 = V_CMPX_LE_F16_e32
18907   { 2845,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #2845 = V_CMPX_LE_F16_sdwa
18908   { 2846,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2846 = V_CMPX_LE_F32_e32
18913   { 2851,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2851 = V_CMPX_LE_F32_sdwa
18914   { 2852,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2852 = V_CMPX_LE_F64_e32
18918   { 2856,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2856 = V_CMPX_LE_I16_e32
18923   { 2861,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2861 = V_CMPX_LE_I16_sdwa
18924   { 2862,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2862 = V_CMPX_LE_I32_e32
18929   { 2867,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2867 = V_CMPX_LE_I32_sdwa
18930   { 2868,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2868 = V_CMPX_LE_I64_e32
18934   { 2872,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2872 = V_CMPX_LE_U16_e32
18939   { 2877,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2877 = V_CMPX_LE_U16_sdwa
18940   { 2878,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2878 = V_CMPX_LE_U32_e32
18945   { 2883,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2883 = V_CMPX_LE_U32_sdwa
18946   { 2884,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2884 = V_CMPX_LE_U64_e32
18950   { 2888,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #2888 = V_CMPX_LG_F16_e32
18955   { 2893,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #2893 = V_CMPX_LG_F16_sdwa
18956   { 2894,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2894 = V_CMPX_LG_F32_e32
18961   { 2899,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2899 = V_CMPX_LG_F32_sdwa
18962   { 2900,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2900 = V_CMPX_LG_F64_e32
18966   { 2904,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #2904 = V_CMPX_LT_F16_e32
18971   { 2909,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #2909 = V_CMPX_LT_F16_sdwa
18972   { 2910,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2910 = V_CMPX_LT_F32_e32
18977   { 2915,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2915 = V_CMPX_LT_F32_sdwa
18978   { 2916,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2916 = V_CMPX_LT_F64_e32
18982   { 2920,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2920 = V_CMPX_LT_I16_e32
18987   { 2925,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2925 = V_CMPX_LT_I16_sdwa
18988   { 2926,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2926 = V_CMPX_LT_I32_e32
18993   { 2931,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2931 = V_CMPX_LT_I32_sdwa
18994   { 2932,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2932 = V_CMPX_LT_I64_e32
18998   { 2936,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2936 = V_CMPX_LT_U16_e32
19003   { 2941,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2941 = V_CMPX_LT_U16_sdwa
19004   { 2942,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2942 = V_CMPX_LT_U32_e32
19009   { 2947,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2947 = V_CMPX_LT_U32_sdwa
19010   { 2948,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2948 = V_CMPX_LT_U64_e32
19014   { 2952,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #2952 = V_CMPX_NEQ_F16_e32
19019   { 2957,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #2957 = V_CMPX_NEQ_F16_sdwa
19020   { 2958,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #2958 = V_CMPX_NEQ_F32_e32
19025   { 2963,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #2963 = V_CMPX_NEQ_F32_sdwa
19026   { 2964,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #2964 = V_CMPX_NEQ_F64_e32
19030   { 2968,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2968 = V_CMPX_NE_I16_e32
19035   { 2973,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2973 = V_CMPX_NE_I16_sdwa
19036   { 2974,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2974 = V_CMPX_NE_I32_e32
19041   { 2979,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2979 = V_CMPX_NE_I32_sdwa
19042   { 2980,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2980 = V_CMPX_NE_I64_e32
19046   { 2984,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #2984 = V_CMPX_NE_U16_e32
19051   { 2989,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #2989 = V_CMPX_NE_U16_sdwa
19052   { 2990,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #2990 = V_CMPX_NE_U32_e32
19057   { 2995,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #2995 = V_CMPX_NE_U32_sdwa
19058   { 2996,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #2996 = V_CMPX_NE_U64_e32
19062   { 3000,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #3000 = V_CMPX_NGE_F16_e32
19067   { 3005,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #3005 = V_CMPX_NGE_F16_sdwa
19068   { 3006,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #3006 = V_CMPX_NGE_F32_e32
19073   { 3011,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #3011 = V_CMPX_NGE_F32_sdwa
19074   { 3012,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #3012 = V_CMPX_NGE_F64_e32
19078   { 3016,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #3016 = V_CMPX_NGT_F16_e32
19083   { 3021,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #3021 = V_CMPX_NGT_F16_sdwa
19084   { 3022,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #3022 = V_CMPX_NGT_F32_e32
19089   { 3027,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #3027 = V_CMPX_NGT_F32_sdwa
19090   { 3028,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #3028 = V_CMPX_NGT_F64_e32
19094   { 3032,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #3032 = V_CMPX_NLE_F16_e32
19099   { 3037,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #3037 = V_CMPX_NLE_F16_sdwa
19100   { 3038,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #3038 = V_CMPX_NLE_F32_e32
19105   { 3043,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #3043 = V_CMPX_NLE_F32_sdwa
19106   { 3044,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #3044 = V_CMPX_NLE_F64_e32
19110   { 3048,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #3048 = V_CMPX_NLG_F16_e32
19115   { 3053,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #3053 = V_CMPX_NLG_F16_sdwa
19116   { 3054,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #3054 = V_CMPX_NLG_F32_e32
19121   { 3059,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #3059 = V_CMPX_NLG_F32_sdwa
19122   { 3060,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #3060 = V_CMPX_NLG_F64_e32
19126   { 3064,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #3064 = V_CMPX_NLT_F16_e32
19131   { 3069,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #3069 = V_CMPX_NLT_F16_sdwa
19132   { 3070,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #3070 = V_CMPX_NLT_F32_e32
19137   { 3075,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #3075 = V_CMPX_NLT_F32_sdwa
19138   { 3076,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #3076 = V_CMPX_NLT_F64_e32
19142   { 3080,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #3080 = V_CMPX_O_F16_e32
19147   { 3085,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #3085 = V_CMPX_O_F16_sdwa
19148   { 3086,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #3086 = V_CMPX_O_F32_e32
19153   { 3091,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #3091 = V_CMPX_O_F32_sdwa
19154   { 3092,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #3092 = V_CMPX_O_F64_e32
19158   { 3096,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #3096 = V_CMPX_TRU_F16_e32
19163   { 3101,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #3101 = V_CMPX_TRU_F16_sdwa
19164   { 3102,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #3102 = V_CMPX_TRU_F32_e32
19169   { 3107,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #3107 = V_CMPX_TRU_F32_sdwa
19170   { 3108,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #3108 = V_CMPX_TRU_F64_e32
19174   { 3112,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #3112 = V_CMPX_T_I16_e32
19179   { 3117,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #3117 = V_CMPX_T_I16_sdwa
19180   { 3118,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #3118 = V_CMPX_T_I32_e32
19185   { 3123,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #3123 = V_CMPX_T_I32_sdwa
19186   { 3124,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #3124 = V_CMPX_T_I64_e32
19190   { 3128,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #3128 = V_CMPX_T_U16_e32
19195   { 3133,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #3133 = V_CMPX_T_U16_sdwa
19196   { 3134,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #3134 = V_CMPX_T_U32_e32
19201   { 3139,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #3139 = V_CMPX_T_U32_sdwa
19202   { 3140,	2,	0,	4,	11,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #3140 = V_CMPX_T_U64_e32
19206   { 3144,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #3144 = V_CMPX_U_F16_e32
19211   { 3149,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #3149 = V_CMPX_U_F16_sdwa
19212   { 3150,	2,	0,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #3150 = V_CMPX_U_F32_e32
19217   { 3155,	8,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #3155 = V_CMPX_U_F32_sdwa
19218   { 3156,	2,	0,	4,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #3156 = V_CMPX_U_F64_e32
19486   { 3424,	10,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList13, nullptr, OperandInfo281, -1 ,nullptr },  // Inst #3424 = V_CNDMASK_B32_dpp
19487   { 3425,	3,	1,	4,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList13, nullptr, OperandInfo278, -1 ,nullptr },  // Inst #3425 = V_CNDMASK_B32_e32
19489   { 3427,	10,	1,	8,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr },  // Inst #3427 = V_CNDMASK_B32_sdwa
19610   { 3548,	9,	1,	8,	14,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList13, nullptr, OperandInfo345, -1 ,nullptr },  // Inst #3548 = V_DIV_FMAS_F32
19611   { 3549,	9,	1,	8,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList13, nullptr, OperandInfo363, -1 ,nullptr },  // Inst #3549 = V_DIV_FMAS_F64
20109   { 4047,	8,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #4047 = V_SUBBREV_U32_dpp
20110   { 4048,	3,	1,	4,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #4048 = V_SUBBREV_U32_e32
20112   { 4050,	10,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #4050 = V_SUBBREV_U32_sdwa
20113   { 4051,	8,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #4051 = V_SUBB_U32_dpp
20114   { 4052,	3,	1,	4,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #4052 = V_SUBB_U32_e32
20116   { 4054,	10,	1,	8,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #4054 = V_SUBB_U32_sdwa
27964   { 11902,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #11902 = V_ADDC_CO_U32_dpp_gfx9
27965   { 11903,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11903 = V_ADDC_CO_U32_e32_gfx9
27967   { 11905,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11905 = V_ADDC_CO_U32_sdwa_gfx9
27968   { 11906,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #11906 = V_ADDC_U32_dpp_vi
27969   { 11907,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11907 = V_ADDC_U32_e32_gfx6_gfx7
27970   { 11908,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11908 = V_ADDC_U32_e32_vi
27973   { 11911,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11911 = V_ADDC_U32_sdwa_vi
27974   { 11912,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #11912 = V_ADD_CO_CI_U32_dpp8_gfx10
27975   { 11913,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #11913 = V_ADD_CO_CI_U32_dpp8_w32_gfx10
27976   { 11914,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #11914 = V_ADD_CO_CI_U32_dpp8_w64_gfx10
27977   { 11915,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #11915 = V_ADD_CO_CI_U32_dpp_gfx10
27978   { 11916,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #11916 = V_ADD_CO_CI_U32_dpp_w32_gfx10
27979   { 11917,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #11917 = V_ADD_CO_CI_U32_dpp_w64_gfx10
27980   { 11918,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #11918 = V_ADD_CO_CI_U32_e32_gfx10
27982   { 11920,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11920 = V_ADD_CO_CI_U32_sdwa_gfx10
27983   { 11921,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11921 = V_ADD_CO_CI_U32_sdwa_w32_gfx10
27984   { 11922,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #11922 = V_ADD_CO_CI_U32_sdwa_w64_gfx10
28148   { 12086,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12086 = V_CMPSX_EQ_F32_e32_gfx6_gfx7
28150   { 12088,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12088 = V_CMPSX_EQ_F64_e32_gfx6_gfx7
28152   { 12090,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12090 = V_CMPSX_F_F32_e32_gfx6_gfx7
28154   { 12092,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12092 = V_CMPSX_F_F64_e32_gfx6_gfx7
28156   { 12094,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12094 = V_CMPSX_GE_F32_e32_gfx6_gfx7
28158   { 12096,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12096 = V_CMPSX_GE_F64_e32_gfx6_gfx7
28160   { 12098,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12098 = V_CMPSX_GT_F32_e32_gfx6_gfx7
28162   { 12100,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12100 = V_CMPSX_GT_F64_e32_gfx6_gfx7
28164   { 12102,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12102 = V_CMPSX_LE_F32_e32_gfx6_gfx7
28166   { 12104,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12104 = V_CMPSX_LE_F64_e32_gfx6_gfx7
28168   { 12106,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12106 = V_CMPSX_LG_F32_e32_gfx6_gfx7
28170   { 12108,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12108 = V_CMPSX_LG_F64_e32_gfx6_gfx7
28172   { 12110,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12110 = V_CMPSX_LT_F32_e32_gfx6_gfx7
28174   { 12112,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12112 = V_CMPSX_LT_F64_e32_gfx6_gfx7
28176   { 12114,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12114 = V_CMPSX_NEQ_F32_e32_gfx6_gfx7
28178   { 12116,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12116 = V_CMPSX_NEQ_F64_e32_gfx6_gfx7
28180   { 12118,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12118 = V_CMPSX_NGE_F32_e32_gfx6_gfx7
28182   { 12120,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12120 = V_CMPSX_NGE_F64_e32_gfx6_gfx7
28184   { 12122,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12122 = V_CMPSX_NGT_F32_e32_gfx6_gfx7
28186   { 12124,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12124 = V_CMPSX_NGT_F64_e32_gfx6_gfx7
28188   { 12126,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12126 = V_CMPSX_NLE_F32_e32_gfx6_gfx7
28190   { 12128,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12128 = V_CMPSX_NLE_F64_e32_gfx6_gfx7
28192   { 12130,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12130 = V_CMPSX_NLG_F32_e32_gfx6_gfx7
28194   { 12132,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12132 = V_CMPSX_NLG_F64_e32_gfx6_gfx7
28196   { 12134,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12134 = V_CMPSX_NLT_F32_e32_gfx6_gfx7
28198   { 12136,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12136 = V_CMPSX_NLT_F64_e32_gfx6_gfx7
28200   { 12138,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12138 = V_CMPSX_O_F32_e32_gfx6_gfx7
28202   { 12140,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12140 = V_CMPSX_O_F64_e32_gfx6_gfx7
28204   { 12142,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12142 = V_CMPSX_TRU_F32_e32_gfx6_gfx7
28206   { 12144,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12144 = V_CMPSX_TRU_F64_e32_gfx6_gfx7
28208   { 12146,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12146 = V_CMPSX_U_F32_e32_gfx6_gfx7
28210   { 12148,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12148 = V_CMPSX_U_F64_e32_gfx6_gfx7
28277   { 12215,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12215 = V_CMPX_CLASS_F16_e32_vi
28281   { 12219,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12219 = V_CMPX_CLASS_F16_sdwa_gfx9
28282   { 12220,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12220 = V_CMPX_CLASS_F16_sdwa_vi
28284   { 12222,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12222 = V_CMPX_CLASS_F32_e32_gfx6_gfx7
28285   { 12223,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12223 = V_CMPX_CLASS_F32_e32_vi
28290   { 12228,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12228 = V_CMPX_CLASS_F32_sdwa_gfx9
28291   { 12229,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12229 = V_CMPX_CLASS_F32_sdwa_vi
28293   { 12231,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo325, -1 ,nullptr },  // Inst #12231 = V_CMPX_CLASS_F64_e32_gfx6_gfx7
28294   { 12232,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo325, -1 ,nullptr },  // Inst #12232 = V_CMPX_CLASS_F64_e32_vi
28299   { 12237,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12237 = V_CMPX_EQ_F16_e32_vi
28303   { 12241,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12241 = V_CMPX_EQ_F16_sdwa_gfx9
28304   { 12242,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12242 = V_CMPX_EQ_F16_sdwa_vi
28306   { 12244,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12244 = V_CMPX_EQ_F32_e32_gfx6_gfx7
28307   { 12245,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12245 = V_CMPX_EQ_F32_e32_vi
28312   { 12250,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12250 = V_CMPX_EQ_F32_sdwa_gfx9
28313   { 12251,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12251 = V_CMPX_EQ_F32_sdwa_vi
28315   { 12253,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12253 = V_CMPX_EQ_F64_e32_gfx6_gfx7
28316   { 12254,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12254 = V_CMPX_EQ_F64_e32_vi
28321   { 12259,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12259 = V_CMPX_EQ_I16_e32_vi
28325   { 12263,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12263 = V_CMPX_EQ_I16_sdwa_gfx9
28326   { 12264,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12264 = V_CMPX_EQ_I16_sdwa_vi
28328   { 12266,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12266 = V_CMPX_EQ_I32_e32_gfx6_gfx7
28329   { 12267,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12267 = V_CMPX_EQ_I32_e32_vi
28334   { 12272,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12272 = V_CMPX_EQ_I32_sdwa_gfx9
28335   { 12273,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12273 = V_CMPX_EQ_I32_sdwa_vi
28337   { 12275,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12275 = V_CMPX_EQ_I64_e32_gfx6_gfx7
28338   { 12276,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12276 = V_CMPX_EQ_I64_e32_vi
28343   { 12281,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12281 = V_CMPX_EQ_U16_e32_vi
28347   { 12285,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12285 = V_CMPX_EQ_U16_sdwa_gfx9
28348   { 12286,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12286 = V_CMPX_EQ_U16_sdwa_vi
28350   { 12288,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12288 = V_CMPX_EQ_U32_e32_gfx6_gfx7
28351   { 12289,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12289 = V_CMPX_EQ_U32_e32_vi
28356   { 12294,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12294 = V_CMPX_EQ_U32_sdwa_gfx9
28357   { 12295,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12295 = V_CMPX_EQ_U32_sdwa_vi
28359   { 12297,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12297 = V_CMPX_EQ_U64_e32_gfx6_gfx7
28360   { 12298,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12298 = V_CMPX_EQ_U64_e32_vi
28365   { 12303,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12303 = V_CMPX_F_F16_e32_vi
28369   { 12307,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12307 = V_CMPX_F_F16_sdwa_gfx9
28370   { 12308,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12308 = V_CMPX_F_F16_sdwa_vi
28372   { 12310,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12310 = V_CMPX_F_F32_e32_gfx6_gfx7
28373   { 12311,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12311 = V_CMPX_F_F32_e32_vi
28378   { 12316,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12316 = V_CMPX_F_F32_sdwa_gfx9
28379   { 12317,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12317 = V_CMPX_F_F32_sdwa_vi
28381   { 12319,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12319 = V_CMPX_F_F64_e32_gfx6_gfx7
28382   { 12320,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12320 = V_CMPX_F_F64_e32_vi
28386   { 12324,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12324 = V_CMPX_F_I16_e32_vi
28388   { 12326,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12326 = V_CMPX_F_I16_sdwa_gfx9
28389   { 12327,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12327 = V_CMPX_F_I16_sdwa_vi
28391   { 12329,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12329 = V_CMPX_F_I32_e32_gfx6_gfx7
28392   { 12330,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12330 = V_CMPX_F_I32_e32_vi
28397   { 12335,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12335 = V_CMPX_F_I32_sdwa_gfx9
28398   { 12336,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12336 = V_CMPX_F_I32_sdwa_vi
28400   { 12338,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12338 = V_CMPX_F_I64_e32_gfx6_gfx7
28401   { 12339,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12339 = V_CMPX_F_I64_e32_vi
28405   { 12343,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12343 = V_CMPX_F_U16_e32_vi
28407   { 12345,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12345 = V_CMPX_F_U16_sdwa_gfx9
28408   { 12346,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12346 = V_CMPX_F_U16_sdwa_vi
28410   { 12348,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12348 = V_CMPX_F_U32_e32_gfx6_gfx7
28411   { 12349,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12349 = V_CMPX_F_U32_e32_vi
28416   { 12354,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12354 = V_CMPX_F_U32_sdwa_gfx9
28417   { 12355,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12355 = V_CMPX_F_U32_sdwa_vi
28419   { 12357,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12357 = V_CMPX_F_U64_e32_gfx6_gfx7
28420   { 12358,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12358 = V_CMPX_F_U64_e32_vi
28425   { 12363,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12363 = V_CMPX_GE_F16_e32_vi
28429   { 12367,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12367 = V_CMPX_GE_F16_sdwa_gfx9
28430   { 12368,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12368 = V_CMPX_GE_F16_sdwa_vi
28432   { 12370,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12370 = V_CMPX_GE_F32_e32_gfx6_gfx7
28433   { 12371,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12371 = V_CMPX_GE_F32_e32_vi
28438   { 12376,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12376 = V_CMPX_GE_F32_sdwa_gfx9
28439   { 12377,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12377 = V_CMPX_GE_F32_sdwa_vi
28441   { 12379,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12379 = V_CMPX_GE_F64_e32_gfx6_gfx7
28442   { 12380,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12380 = V_CMPX_GE_F64_e32_vi
28447   { 12385,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12385 = V_CMPX_GE_I16_e32_vi
28451   { 12389,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12389 = V_CMPX_GE_I16_sdwa_gfx9
28452   { 12390,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12390 = V_CMPX_GE_I16_sdwa_vi
28454   { 12392,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12392 = V_CMPX_GE_I32_e32_gfx6_gfx7
28455   { 12393,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12393 = V_CMPX_GE_I32_e32_vi
28460   { 12398,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12398 = V_CMPX_GE_I32_sdwa_gfx9
28461   { 12399,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12399 = V_CMPX_GE_I32_sdwa_vi
28463   { 12401,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12401 = V_CMPX_GE_I64_e32_gfx6_gfx7
28464   { 12402,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12402 = V_CMPX_GE_I64_e32_vi
28469   { 12407,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12407 = V_CMPX_GE_U16_e32_vi
28473   { 12411,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12411 = V_CMPX_GE_U16_sdwa_gfx9
28474   { 12412,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12412 = V_CMPX_GE_U16_sdwa_vi
28476   { 12414,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12414 = V_CMPX_GE_U32_e32_gfx6_gfx7
28477   { 12415,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12415 = V_CMPX_GE_U32_e32_vi
28482   { 12420,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12420 = V_CMPX_GE_U32_sdwa_gfx9
28483   { 12421,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12421 = V_CMPX_GE_U32_sdwa_vi
28485   { 12423,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12423 = V_CMPX_GE_U64_e32_gfx6_gfx7
28486   { 12424,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12424 = V_CMPX_GE_U64_e32_vi
28491   { 12429,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12429 = V_CMPX_GT_F16_e32_vi
28495   { 12433,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12433 = V_CMPX_GT_F16_sdwa_gfx9
28496   { 12434,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12434 = V_CMPX_GT_F16_sdwa_vi
28498   { 12436,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12436 = V_CMPX_GT_F32_e32_gfx6_gfx7
28499   { 12437,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12437 = V_CMPX_GT_F32_e32_vi
28504   { 12442,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12442 = V_CMPX_GT_F32_sdwa_gfx9
28505   { 12443,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12443 = V_CMPX_GT_F32_sdwa_vi
28507   { 12445,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12445 = V_CMPX_GT_F64_e32_gfx6_gfx7
28508   { 12446,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12446 = V_CMPX_GT_F64_e32_vi
28513   { 12451,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12451 = V_CMPX_GT_I16_e32_vi
28517   { 12455,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12455 = V_CMPX_GT_I16_sdwa_gfx9
28518   { 12456,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12456 = V_CMPX_GT_I16_sdwa_vi
28520   { 12458,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12458 = V_CMPX_GT_I32_e32_gfx6_gfx7
28521   { 12459,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12459 = V_CMPX_GT_I32_e32_vi
28526   { 12464,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12464 = V_CMPX_GT_I32_sdwa_gfx9
28527   { 12465,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12465 = V_CMPX_GT_I32_sdwa_vi
28529   { 12467,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12467 = V_CMPX_GT_I64_e32_gfx6_gfx7
28530   { 12468,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12468 = V_CMPX_GT_I64_e32_vi
28535   { 12473,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12473 = V_CMPX_GT_U16_e32_vi
28539   { 12477,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12477 = V_CMPX_GT_U16_sdwa_gfx9
28540   { 12478,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12478 = V_CMPX_GT_U16_sdwa_vi
28542   { 12480,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12480 = V_CMPX_GT_U32_e32_gfx6_gfx7
28543   { 12481,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12481 = V_CMPX_GT_U32_e32_vi
28548   { 12486,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12486 = V_CMPX_GT_U32_sdwa_gfx9
28549   { 12487,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12487 = V_CMPX_GT_U32_sdwa_vi
28551   { 12489,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12489 = V_CMPX_GT_U64_e32_gfx6_gfx7
28552   { 12490,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12490 = V_CMPX_GT_U64_e32_vi
28557   { 12495,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12495 = V_CMPX_LE_F16_e32_vi
28561   { 12499,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12499 = V_CMPX_LE_F16_sdwa_gfx9
28562   { 12500,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12500 = V_CMPX_LE_F16_sdwa_vi
28564   { 12502,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12502 = V_CMPX_LE_F32_e32_gfx6_gfx7
28565   { 12503,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12503 = V_CMPX_LE_F32_e32_vi
28570   { 12508,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12508 = V_CMPX_LE_F32_sdwa_gfx9
28571   { 12509,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12509 = V_CMPX_LE_F32_sdwa_vi
28573   { 12511,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12511 = V_CMPX_LE_F64_e32_gfx6_gfx7
28574   { 12512,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12512 = V_CMPX_LE_F64_e32_vi
28579   { 12517,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12517 = V_CMPX_LE_I16_e32_vi
28583   { 12521,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12521 = V_CMPX_LE_I16_sdwa_gfx9
28584   { 12522,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12522 = V_CMPX_LE_I16_sdwa_vi
28586   { 12524,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12524 = V_CMPX_LE_I32_e32_gfx6_gfx7
28587   { 12525,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12525 = V_CMPX_LE_I32_e32_vi
28592   { 12530,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12530 = V_CMPX_LE_I32_sdwa_gfx9
28593   { 12531,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12531 = V_CMPX_LE_I32_sdwa_vi
28595   { 12533,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12533 = V_CMPX_LE_I64_e32_gfx6_gfx7
28596   { 12534,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12534 = V_CMPX_LE_I64_e32_vi
28601   { 12539,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12539 = V_CMPX_LE_U16_e32_vi
28605   { 12543,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12543 = V_CMPX_LE_U16_sdwa_gfx9
28606   { 12544,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12544 = V_CMPX_LE_U16_sdwa_vi
28608   { 12546,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12546 = V_CMPX_LE_U32_e32_gfx6_gfx7
28609   { 12547,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12547 = V_CMPX_LE_U32_e32_vi
28614   { 12552,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12552 = V_CMPX_LE_U32_sdwa_gfx9
28615   { 12553,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12553 = V_CMPX_LE_U32_sdwa_vi
28617   { 12555,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12555 = V_CMPX_LE_U64_e32_gfx6_gfx7
28618   { 12556,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12556 = V_CMPX_LE_U64_e32_vi
28623   { 12561,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12561 = V_CMPX_LG_F16_e32_vi
28627   { 12565,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12565 = V_CMPX_LG_F16_sdwa_gfx9
28628   { 12566,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12566 = V_CMPX_LG_F16_sdwa_vi
28630   { 12568,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12568 = V_CMPX_LG_F32_e32_gfx6_gfx7
28631   { 12569,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12569 = V_CMPX_LG_F32_e32_vi
28636   { 12574,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12574 = V_CMPX_LG_F32_sdwa_gfx9
28637   { 12575,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12575 = V_CMPX_LG_F32_sdwa_vi
28639   { 12577,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12577 = V_CMPX_LG_F64_e32_gfx6_gfx7
28640   { 12578,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12578 = V_CMPX_LG_F64_e32_vi
28645   { 12583,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12583 = V_CMPX_LT_F16_e32_vi
28649   { 12587,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12587 = V_CMPX_LT_F16_sdwa_gfx9
28650   { 12588,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12588 = V_CMPX_LT_F16_sdwa_vi
28652   { 12590,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12590 = V_CMPX_LT_F32_e32_gfx6_gfx7
28653   { 12591,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12591 = V_CMPX_LT_F32_e32_vi
28658   { 12596,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12596 = V_CMPX_LT_F32_sdwa_gfx9
28659   { 12597,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12597 = V_CMPX_LT_F32_sdwa_vi
28661   { 12599,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12599 = V_CMPX_LT_F64_e32_gfx6_gfx7
28662   { 12600,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12600 = V_CMPX_LT_F64_e32_vi
28667   { 12605,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12605 = V_CMPX_LT_I16_e32_vi
28671   { 12609,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12609 = V_CMPX_LT_I16_sdwa_gfx9
28672   { 12610,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12610 = V_CMPX_LT_I16_sdwa_vi
28674   { 12612,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12612 = V_CMPX_LT_I32_e32_gfx6_gfx7
28675   { 12613,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12613 = V_CMPX_LT_I32_e32_vi
28680   { 12618,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12618 = V_CMPX_LT_I32_sdwa_gfx9
28681   { 12619,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12619 = V_CMPX_LT_I32_sdwa_vi
28683   { 12621,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12621 = V_CMPX_LT_I64_e32_gfx6_gfx7
28684   { 12622,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12622 = V_CMPX_LT_I64_e32_vi
28689   { 12627,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12627 = V_CMPX_LT_U16_e32_vi
28693   { 12631,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12631 = V_CMPX_LT_U16_sdwa_gfx9
28694   { 12632,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12632 = V_CMPX_LT_U16_sdwa_vi
28696   { 12634,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12634 = V_CMPX_LT_U32_e32_gfx6_gfx7
28697   { 12635,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12635 = V_CMPX_LT_U32_e32_vi
28702   { 12640,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12640 = V_CMPX_LT_U32_sdwa_gfx9
28703   { 12641,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12641 = V_CMPX_LT_U32_sdwa_vi
28705   { 12643,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12643 = V_CMPX_LT_U64_e32_gfx6_gfx7
28706   { 12644,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12644 = V_CMPX_LT_U64_e32_vi
28711   { 12649,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12649 = V_CMPX_NEQ_F16_e32_vi
28715   { 12653,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12653 = V_CMPX_NEQ_F16_sdwa_gfx9
28716   { 12654,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12654 = V_CMPX_NEQ_F16_sdwa_vi
28718   { 12656,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12656 = V_CMPX_NEQ_F32_e32_gfx6_gfx7
28719   { 12657,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12657 = V_CMPX_NEQ_F32_e32_vi
28724   { 12662,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12662 = V_CMPX_NEQ_F32_sdwa_gfx9
28725   { 12663,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12663 = V_CMPX_NEQ_F32_sdwa_vi
28727   { 12665,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12665 = V_CMPX_NEQ_F64_e32_gfx6_gfx7
28728   { 12666,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12666 = V_CMPX_NEQ_F64_e32_vi
28733   { 12671,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12671 = V_CMPX_NE_I16_e32_vi
28737   { 12675,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12675 = V_CMPX_NE_I16_sdwa_gfx9
28738   { 12676,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12676 = V_CMPX_NE_I16_sdwa_vi
28740   { 12678,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12678 = V_CMPX_NE_I32_e32_gfx6_gfx7
28741   { 12679,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12679 = V_CMPX_NE_I32_e32_vi
28746   { 12684,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12684 = V_CMPX_NE_I32_sdwa_gfx9
28747   { 12685,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12685 = V_CMPX_NE_I32_sdwa_vi
28749   { 12687,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12687 = V_CMPX_NE_I64_e32_gfx6_gfx7
28750   { 12688,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12688 = V_CMPX_NE_I64_e32_vi
28755   { 12693,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12693 = V_CMPX_NE_U16_e32_vi
28759   { 12697,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12697 = V_CMPX_NE_U16_sdwa_gfx9
28760   { 12698,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12698 = V_CMPX_NE_U16_sdwa_vi
28762   { 12700,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12700 = V_CMPX_NE_U32_e32_gfx6_gfx7
28763   { 12701,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12701 = V_CMPX_NE_U32_e32_vi
28768   { 12706,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12706 = V_CMPX_NE_U32_sdwa_gfx9
28769   { 12707,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12707 = V_CMPX_NE_U32_sdwa_vi
28771   { 12709,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12709 = V_CMPX_NE_U64_e32_gfx6_gfx7
28772   { 12710,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12710 = V_CMPX_NE_U64_e32_vi
28777   { 12715,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12715 = V_CMPX_NGE_F16_e32_vi
28781   { 12719,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12719 = V_CMPX_NGE_F16_sdwa_gfx9
28782   { 12720,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12720 = V_CMPX_NGE_F16_sdwa_vi
28784   { 12722,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12722 = V_CMPX_NGE_F32_e32_gfx6_gfx7
28785   { 12723,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12723 = V_CMPX_NGE_F32_e32_vi
28790   { 12728,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12728 = V_CMPX_NGE_F32_sdwa_gfx9
28791   { 12729,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12729 = V_CMPX_NGE_F32_sdwa_vi
28793   { 12731,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12731 = V_CMPX_NGE_F64_e32_gfx6_gfx7
28794   { 12732,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12732 = V_CMPX_NGE_F64_e32_vi
28799   { 12737,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12737 = V_CMPX_NGT_F16_e32_vi
28803   { 12741,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12741 = V_CMPX_NGT_F16_sdwa_gfx9
28804   { 12742,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12742 = V_CMPX_NGT_F16_sdwa_vi
28806   { 12744,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12744 = V_CMPX_NGT_F32_e32_gfx6_gfx7
28807   { 12745,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12745 = V_CMPX_NGT_F32_e32_vi
28812   { 12750,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12750 = V_CMPX_NGT_F32_sdwa_gfx9
28813   { 12751,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12751 = V_CMPX_NGT_F32_sdwa_vi
28815   { 12753,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12753 = V_CMPX_NGT_F64_e32_gfx6_gfx7
28816   { 12754,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12754 = V_CMPX_NGT_F64_e32_vi
28821   { 12759,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12759 = V_CMPX_NLE_F16_e32_vi
28825   { 12763,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12763 = V_CMPX_NLE_F16_sdwa_gfx9
28826   { 12764,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12764 = V_CMPX_NLE_F16_sdwa_vi
28828   { 12766,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12766 = V_CMPX_NLE_F32_e32_gfx6_gfx7
28829   { 12767,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12767 = V_CMPX_NLE_F32_e32_vi
28834   { 12772,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12772 = V_CMPX_NLE_F32_sdwa_gfx9
28835   { 12773,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12773 = V_CMPX_NLE_F32_sdwa_vi
28837   { 12775,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12775 = V_CMPX_NLE_F64_e32_gfx6_gfx7
28838   { 12776,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12776 = V_CMPX_NLE_F64_e32_vi
28843   { 12781,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12781 = V_CMPX_NLG_F16_e32_vi
28847   { 12785,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12785 = V_CMPX_NLG_F16_sdwa_gfx9
28848   { 12786,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12786 = V_CMPX_NLG_F16_sdwa_vi
28850   { 12788,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12788 = V_CMPX_NLG_F32_e32_gfx6_gfx7
28851   { 12789,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12789 = V_CMPX_NLG_F32_e32_vi
28856   { 12794,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12794 = V_CMPX_NLG_F32_sdwa_gfx9
28857   { 12795,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12795 = V_CMPX_NLG_F32_sdwa_vi
28859   { 12797,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12797 = V_CMPX_NLG_F64_e32_gfx6_gfx7
28860   { 12798,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12798 = V_CMPX_NLG_F64_e32_vi
28865   { 12803,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12803 = V_CMPX_NLT_F16_e32_vi
28869   { 12807,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12807 = V_CMPX_NLT_F16_sdwa_gfx9
28870   { 12808,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12808 = V_CMPX_NLT_F16_sdwa_vi
28872   { 12810,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12810 = V_CMPX_NLT_F32_e32_gfx6_gfx7
28873   { 12811,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12811 = V_CMPX_NLT_F32_e32_vi
28878   { 12816,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12816 = V_CMPX_NLT_F32_sdwa_gfx9
28879   { 12817,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12817 = V_CMPX_NLT_F32_sdwa_vi
28881   { 12819,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12819 = V_CMPX_NLT_F64_e32_gfx6_gfx7
28882   { 12820,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12820 = V_CMPX_NLT_F64_e32_vi
28887   { 12825,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12825 = V_CMPX_O_F16_e32_vi
28891   { 12829,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12829 = V_CMPX_O_F16_sdwa_gfx9
28892   { 12830,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12830 = V_CMPX_O_F16_sdwa_vi
28894   { 12832,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12832 = V_CMPX_O_F32_e32_gfx6_gfx7
28895   { 12833,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12833 = V_CMPX_O_F32_e32_vi
28900   { 12838,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12838 = V_CMPX_O_F32_sdwa_gfx9
28901   { 12839,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12839 = V_CMPX_O_F32_sdwa_vi
28903   { 12841,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12841 = V_CMPX_O_F64_e32_gfx6_gfx7
28904   { 12842,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12842 = V_CMPX_O_F64_e32_vi
28909   { 12847,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12847 = V_CMPX_TRU_F16_e32_vi
28913   { 12851,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12851 = V_CMPX_TRU_F16_sdwa_gfx9
28914   { 12852,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12852 = V_CMPX_TRU_F16_sdwa_vi
28916   { 12854,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12854 = V_CMPX_TRU_F32_e32_gfx6_gfx7
28917   { 12855,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12855 = V_CMPX_TRU_F32_e32_vi
28922   { 12860,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12860 = V_CMPX_TRU_F32_sdwa_gfx9
28923   { 12861,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12861 = V_CMPX_TRU_F32_sdwa_vi
28925   { 12863,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12863 = V_CMPX_TRU_F64_e32_gfx6_gfx7
28926   { 12864,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12864 = V_CMPX_TRU_F64_e32_vi
28930   { 12868,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12868 = V_CMPX_T_I16_e32_vi
28932   { 12870,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12870 = V_CMPX_T_I16_sdwa_gfx9
28933   { 12871,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12871 = V_CMPX_T_I16_sdwa_vi
28935   { 12873,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12873 = V_CMPX_T_I32_e32_gfx6_gfx7
28936   { 12874,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12874 = V_CMPX_T_I32_e32_vi
28941   { 12879,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12879 = V_CMPX_T_I32_sdwa_gfx9
28942   { 12880,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12880 = V_CMPX_T_I32_sdwa_vi
28944   { 12882,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12882 = V_CMPX_T_I64_e32_gfx6_gfx7
28945   { 12883,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12883 = V_CMPX_T_I64_e32_vi
28949   { 12887,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr },  // Inst #12887 = V_CMPX_T_U16_e32_vi
28951   { 12889,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12889 = V_CMPX_T_U16_sdwa_gfx9
28952   { 12890,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr },  // Inst #12890 = V_CMPX_T_U16_sdwa_vi
28954   { 12892,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12892 = V_CMPX_T_U32_e32_gfx6_gfx7
28955   { 12893,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr },  // Inst #12893 = V_CMPX_T_U32_e32_vi
28960   { 12898,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12898 = V_CMPX_T_U32_sdwa_gfx9
28961   { 12899,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr },  // Inst #12899 = V_CMPX_T_U32_sdwa_vi
28963   { 12901,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12901 = V_CMPX_T_U64_e32_gfx6_gfx7
28964   { 12902,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr },  // Inst #12902 = V_CMPX_T_U64_e32_vi
28969   { 12907,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr },  // Inst #12907 = V_CMPX_U_F16_e32_vi
28973   { 12911,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12911 = V_CMPX_U_F16_sdwa_gfx9
28974   { 12912,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr },  // Inst #12912 = V_CMPX_U_F16_sdwa_vi
28976   { 12914,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12914 = V_CMPX_U_F32_e32_gfx6_gfx7
28977   { 12915,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr },  // Inst #12915 = V_CMPX_U_F32_e32_vi
28982   { 12920,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12920 = V_CMPX_U_F32_sdwa_gfx9
28983   { 12921,	8,	1,	8,	2,	0, 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr },  // Inst #12921 = V_CMPX_U_F32_sdwa_vi
28985   { 12923,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12923 = V_CMPX_U_F64_e32_gfx6_gfx7
28986   { 12924,	2,	0,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr },  // Inst #12924 = V_CMPX_U_F64_e32_vi
29704   { 13642,	6,	1,	8,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo709, -1 ,nullptr },  // Inst #13642 = V_CNDMASK_B32_dpp8_gfx10
29705   { 13643,	6,	1,	8,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo709, -1 ,nullptr },  // Inst #13643 = V_CNDMASK_B32_dpp8_w32_gfx10
29706   { 13644,	6,	1,	8,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo709, -1 ,nullptr },  // Inst #13644 = V_CNDMASK_B32_dpp8_w64_gfx10
29707   { 13645,	11,	1,	8,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo711, -1 ,nullptr },  // Inst #13645 = V_CNDMASK_B32_dpp_gfx10
29708   { 13646,	10,	1,	8,	2,	0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList13, nullptr, OperandInfo281, -1 ,nullptr },  // Inst #13646 = V_CNDMASK_B32_dpp_vi
29709   { 13647,	11,	1,	8,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo711, -1 ,nullptr },  // Inst #13647 = V_CNDMASK_B32_dpp_w32_gfx10
29710   { 13648,	11,	1,	8,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo711, -1 ,nullptr },  // Inst #13648 = V_CNDMASK_B32_dpp_w64_gfx10
29711   { 13649,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList13, nullptr, OperandInfo278, -1 ,nullptr },  // Inst #13649 = V_CNDMASK_B32_e32_gfx10
29712   { 13650,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList13, nullptr, OperandInfo278, -1 ,nullptr },  // Inst #13650 = V_CNDMASK_B32_e32_gfx6_gfx7
29713   { 13651,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x102ULL, ImplicitList13, nullptr, OperandInfo278, -1 ,nullptr },  // Inst #13651 = V_CNDMASK_B32_e32_vi
29717   { 13655,	10,	1,	8,	2,	0, 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr },  // Inst #13655 = V_CNDMASK_B32_sdwa_gfx10
29718   { 13656,	10,	1,	8,	2,	0, 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr },  // Inst #13656 = V_CNDMASK_B32_sdwa_gfx9
29719   { 13657,	10,	1,	8,	2,	0, 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr },  // Inst #13657 = V_CNDMASK_B32_sdwa_vi
29720   { 13658,	10,	1,	8,	2,	0, 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr },  // Inst #13658 = V_CNDMASK_B32_sdwa_w32_gfx10
29721   { 13659,	10,	1,	8,	2,	0, 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr },  // Inst #13659 = V_CNDMASK_B32_sdwa_w64_gfx10
30049   { 13987,	9,	1,	8,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList13, nullptr, OperandInfo345, -1 ,nullptr },  // Inst #13987 = V_DIV_FMAS_F32_gfx10
30050   { 13988,	9,	1,	8,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList13, nullptr, OperandInfo345, -1 ,nullptr },  // Inst #13988 = V_DIV_FMAS_F32_gfx6_gfx7
30051   { 13989,	9,	1,	8,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0xa00000000402ULL, ImplicitList13, nullptr, OperandInfo345, -1 ,nullptr },  // Inst #13989 = V_DIV_FMAS_F32_vi
30052   { 13990,	9,	1,	8,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList13, nullptr, OperandInfo363, -1 ,nullptr },  // Inst #13990 = V_DIV_FMAS_F64_gfx10
30053   { 13991,	9,	1,	8,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList13, nullptr, OperandInfo363, -1 ,nullptr },  // Inst #13991 = V_DIV_FMAS_F64_gfx6_gfx7
30054   { 13992,	9,	1,	8,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x10a00000000402ULL, ImplicitList13, nullptr, OperandInfo363, -1 ,nullptr },  // Inst #13992 = V_DIV_FMAS_F64_vi
31122   { 15060,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15060 = V_SUBBREV_CO_U32_dpp_gfx9
31123   { 15061,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15061 = V_SUBBREV_CO_U32_e32_gfx9
31125   { 15063,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15063 = V_SUBBREV_CO_U32_sdwa_gfx9
31126   { 15064,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15064 = V_SUBBREV_U32_dpp_vi
31127   { 15065,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15065 = V_SUBBREV_U32_e32_gfx6_gfx7
31128   { 15066,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15066 = V_SUBBREV_U32_e32_vi
31131   { 15069,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15069 = V_SUBBREV_U32_sdwa_vi
31132   { 15070,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15070 = V_SUBB_CO_U32_dpp_gfx9
31133   { 15071,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15071 = V_SUBB_CO_U32_e32_gfx9
31135   { 15073,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15073 = V_SUBB_CO_U32_sdwa_gfx9
31136   { 15074,	8,	1,	8,	9,	0|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr },  // Inst #15074 = V_SUBB_U32_dpp_vi
31137   { 15075,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15075 = V_SUBB_U32_e32_gfx6_gfx7
31138   { 15076,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15076 = V_SUBB_U32_e32_vi
31141   { 15079,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15079 = V_SUBB_U32_sdwa_vi
31142   { 15080,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15080 = V_SUBREV_CO_CI_U32_dpp8_gfx10
31143   { 15081,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15081 = V_SUBREV_CO_CI_U32_dpp8_w32_gfx10
31144   { 15082,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15082 = V_SUBREV_CO_CI_U32_dpp8_w64_gfx10
31145   { 15083,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15083 = V_SUBREV_CO_CI_U32_dpp_gfx10
31146   { 15084,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15084 = V_SUBREV_CO_CI_U32_dpp_w32_gfx10
31147   { 15085,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15085 = V_SUBREV_CO_CI_U32_dpp_w64_gfx10
31148   { 15086,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15086 = V_SUBREV_CO_CI_U32_e32_gfx10
31150   { 15088,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15088 = V_SUBREV_CO_CI_U32_sdwa_gfx10
31151   { 15089,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15089 = V_SUBREV_CO_CI_U32_sdwa_w32_gfx10
31152   { 15090,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15090 = V_SUBREV_CO_CI_U32_sdwa_w64_gfx10
31200   { 15138,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15138 = V_SUB_CO_CI_U32_dpp8_gfx10
31201   { 15139,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15139 = V_SUB_CO_CI_U32_dpp8_w32_gfx10
31202   { 15140,	6,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr },  // Inst #15140 = V_SUB_CO_CI_U32_dpp8_w64_gfx10
31203   { 15141,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15141 = V_SUB_CO_CI_U32_dpp_gfx10
31204   { 15142,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15142 = V_SUB_CO_CI_U32_dpp_w32_gfx10
31205   { 15143,	9,	1,	8,	9,	0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr },  // Inst #15143 = V_SUB_CO_CI_U32_dpp_w64_gfx10
31206   { 15144,	3,	1,	4,	2,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr },  // Inst #15144 = V_SUB_CO_CI_U32_e32_gfx10
31208   { 15146,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15146 = V_SUB_CO_CI_U32_sdwa_gfx10
31209   { 15147,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15147 = V_SUB_CO_CI_U32_sdwa_w32_gfx10
31210   { 15148,	10,	1,	8,	9,	0, 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr },  // Inst #15148 = V_SUB_CO_CI_U32_sdwa_w64_gfx10