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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18113 { 2051, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2051 = S_SCRATCH_LOAD_DWORDX2_IMM
18114 { 2052, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2052 = S_SCRATCH_LOAD_DWORDX2_SGPR
18115 { 2053, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2053 = S_SCRATCH_LOAD_DWORDX4_IMM
18116 { 2054, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2054 = S_SCRATCH_LOAD_DWORDX4_SGPR
18117 { 2055, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2055 = S_SCRATCH_LOAD_DWORD_IMM
18118 { 2056, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2056 = S_SCRATCH_LOAD_DWORD_SGPR
18119 { 2057, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2057 = S_SCRATCH_STORE_DWORDX2_IMM
18120 { 2058, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2058 = S_SCRATCH_STORE_DWORDX2_SGPR
18121 { 2059, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2059 = S_SCRATCH_STORE_DWORDX4_IMM
18122 { 2060, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2060 = S_SCRATCH_STORE_DWORDX4_SGPR
18123 { 2061, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2061 = S_SCRATCH_STORE_DWORD_IMM
18124 { 2062, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2062 = S_SCRATCH_STORE_DWORD_SGPR